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PGA2320IDW Datasheet(PDF) 10 Page - Texas Instruments

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Part # PGA2320IDW
Description  Stereo Audio Volume Control
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PGA2320IDW Datasheet(HTML) 10 Page - Texas Instruments

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PGA2320
SBOS312B − JULY 2004 − REVISED DECEMBER 2004
www.ti.com
10
DAISY-CHAINING MULTIPLE
PGA2320 DEVICES
In order to reduce the number of control signals required
to support multiple PGA2320 devices on a printed circuit
board, the serial control port supports daisy-chaining of
multiple
PGA2320
devices.
Figure
4
shows
the
connection requirements for daisy-chain operation. This
arrangement allows a three-wire serial interface to control
many PGA2320 devices.
As shown in Figure 4, the SDO pin from device #1 is
connected to the SDI input of device #2, and is repeated
for additional devices. This configuration in turn forms a
large shift register, in which gain data may be written for all
PGA2320s connected to the serial bus. The length of the
shift register is 16 x N bits, where N is equal to the number
of PGA2320 devices included in the chain. The CS input
must remain low for 16 x N SCLK periods, where N is the
number of devices connected in the chain, in order to allow
enough SCLK cycles to load all devices.
ZERO CROSSING DETECTION
The PGA2320 includes a zero crossing detection function
that can provide for noise-free level transitions. The
concept is to change gain settings on a zero crossing of the
input signal, thus minimizing audible glitches. This
function is enabled or disabled using the ZCEN input
(pin 1). When ZCEN is low, zero crossing detection is
disabled. When ZCEN is high, zero crossing detection will
be enabled.
The zero crossing detection takes effect with a change in
gain setting for a corresponding channel. The new gain
setting will not be latched until either two zero crossings
are detected, or a timeout period of 16ms has elapsed
without detecting two zero crossings. In the case of a
timeout, the new gain setting takes effect with no attempt
to minimize audible artifacts.
SDI
V
INL
V
INR
SDO
SCLK
CS
V
OUTL
V
OUTR
SDI
V
INL
V
INR
SDO
SCLK
CS
V
OUTL
V
OUTR
SDI
V
INL
V
INR
SDO
SCLK
CS
V
OUTL
V
OUTR
Audio
Input
Audio
Input
Audio
Input
100k
100k
Controller
PGA2320
#1
PGA2320
#2
PGA2320
#3
Figure 4. Daisy-Chaining Multiple PGA2320 Devices


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