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FM8PE53B Datasheet(PDF) 10 Page - Feeling Technology Corp. |
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FM8PE53B Datasheet(HTML) 10 Page - Feeling Technology Corp. |
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10 / 53 page  FM8PE53B Web site: http://www.feeling-tech.com.tw Rev1.02.011 Aug 21, 2014 P.10/FM8PE53B FEELING TECHNOLOGY 2.1.5 FSR (Indirect Data Memory Address Pointer) Address Name B7 B6 B5 B4 B3 B2 B1 B0 04h (r/w) FSR * * Indirect data memory address pointer Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description. Bit7:Bit6 : Not used. Read as “1”s. 2.1.6 PORTA, PORTB (Port Data Registers) Address Name B7 B6 B5 B4 B3 B2 B1 B0 05h (r/w) PORTA IOA3 IOA2 IOA1 IOA0 06h (r/w) PORTB IOB7 IOB6 IOB5 IOB4 IOB3 IOB2 IOB1 IOB0 Reading the port (PORTA, PORTB register) reads the status of the pins independent of the pin’s input/output modes. Writing to these ports will write to the port data latch. PORTA is a 4-bit port data Register. Only the low order 4 bits are used (PORTA<3:0>). Bits 7-4 are general purpose read/write bits. IOA3:IOA0 : PORTA I/O pin. = 1, Port pin is high level. = 0, Port pin is low level. IOB7:IOB0 : PORTB I/O pin. = 1, Port pin is high level. = 0, Port pin is low level. Note: IOB3 is open-drain output only if IOSTB3 = 0. See 2.1.17 for detail description. 2.1.7 PCON (Power Control Register) Address Name B7 B6 B5 B4 B3 B2 B1 B0 08h (r/w) PCON WDTE EIS LVDTE * * * * * Bit4:Bit0 : Not used. Read as “1”s. LVDTE : LVDT (low voltage detector) enable bit. = 1, Enable LVDT. = 0, Disable LVDT. EIS : Define the function of IOB0/INT pin. = 1, INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The path of Port B input change of IOB0 pin is masked by hardware, the status of INT pin can also be read by way of reading PORTB. = 0, IOB0 (bi-directional I/O pin) is selected. The path of INT is masked. WDTE : WDT (watch-dog timer) enable bit. = 1, Enable WDT. = 0, Disable WDT. |
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