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FM8PE53B Datasheet(PDF) 33 Page - Feeling Technology Corp. |
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FM8PE53B Datasheet(HTML) 33 Page - Feeling Technology Corp. |
33 / 53 page FM8PE53B Web site: http://www.feeling-tech.com.tw Rev1.02.011 Aug 21, 2014 P.33/FM8PE53B FEELING TECHNOLOGY CLRA Clear ACC Syntax: CLRA Operands: None Operation: 00h ACC; 1 Z Status Affected: Z Description: The ACC register is cleared. Zero bit (Z) is set. Cycles: 1 CLRR Clear R Syntax: CLRR R Operands: 0 R 0x3F Operation: 00h R; 1 Z Status Affected: Z Description: The contents of register ‘R’ are cleared and the Z bit is set. Cycles: 1 CLRWDT Clear Watchdog Timer Syntax: CLRWDT Operands: None Operation: 00h WDT; 00h WDT prescaler (if assigned); 1 TO ̅̅̅̅; 1 PD ̅̅̅̅ Status Affected: TO ̅̅̅̅, PD ̅̅̅̅ Description: The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO ̅̅̅̅ and PD ̅̅̅̅ are set. Cycles: 1 COMR Complement R Syntax: COMR R, d Operands: 0 R 0x3F d [0,1] Operation: R ̅ dest Status Affected: Z Description: The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’. Cycles: 1 DAA Adjust ACC’s data format from HEX to DEC Syntax: DAA Operands: None Operation: ACC(hex) ACC(dec) Status Affected: C Description: Convert the ACC data from hexadecimal to decimal format after any addition operation and restored to ACC. Cycles: 1 |
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