BK3231S Datasheet

V1.5

© 2015 Beken Corporation

Proprietary and Confidential

Page 18 of 24

The local interrupt flag of ADC need not be cleared by software; it will be set after

transform and be cleared after the result has been read out. But the ADC

INTstored ICU should be cleared after the ADC INT service finished.

The range of input voltage is from 0v to 1.5V. If the input voltage more than 1.5V,

a resistor can be added to decrease the input voltage like the next diagram.

PA

D

ADC

Test_point

BK3231

100k

On/off

R1

R2

Note: There are eight GPIO can be ADC input. When used as this:

Voltage=data [9:0]/448; the saturate voltage is 1.5 volt.

3.5 UART

The UART interface has 128 bytes FIFO for both TX and RX. It will generate

interrupt request when there is risk or event of FIFO underflow or overflow. For

the RX, it will generate interrupt if found parity bit check error or stop bit check

error.

When the UART RX line goes from idle state (‘HIGH’) to active state (‘LOW’) for

a set UART clock cycle, it will generate wake up interrupt to activate MCU clock.

3.6 I2C-SMBus

The I2C I/O interface is a two-wire, bi-directional serial bus. The I2C is compliant

with the System Management Bus Specification, version 1.1, and compatible with

the I C serial bus. Reads and writes to the interface by the system controller are

byte oriented with the I2C interface autonomously controlling the serial transfer of

the data.

Data can be transferred at up to 1/10th of the system clock as a master or slave

(this can be faster than allowed by the I2C specification, depending on the

system clock used). A method of extending the clock-low duration is available to

accommodate devices with different speed capabilities on the same bus.