RT8509

8

DS8509-01 March 2012

www.richtek.com

©

Copyright 2012 Richtek Technology Corporation. All rights reserved.

is a registered trademark of Richtek Technology Corporation.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

the ambient temperature, and

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

WDFN-10L 3x3 packages, the thermal resistance,

70

°C/W on a standard JEDEC 51-7 four-layer thermal test

°C can

be calculated by the following formula :

°C − 25°C) / (70°C/W) = 1.429W for

WDFN-10L 3x3 package

The maximum power dissipation depends on the operating

resistance,

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

Figure 2. Derating Curve of Maximum Power Dissipation

Layout Considerations

For high frequency switching power supplies, the PCB

layout is important to get good regulation, high efficiency

and stability. The following descriptions are the guidelines

for better PCB layout.

For good regulation, place the power components as

close as possible. The traces should be wide and short

enough especially for the high current output loop.

The feedback voltage divider resistors must be near the

feedback pin. The divider center trace must be shorter

and the trace must be kept away from any switching

nodes.

The compensation circuit should be kept away from the

power loops and be shielded with a ground trace to

prevent any noise coupling.

Minimize the size of the LX node and keep it wide and

shorter. Keep the LX node away from the FB.

The exposed pad of the chip should be connected to a

strong ground plane for maximum thermal consideration.

Figure 3. PCB Layout Guide

COMP

FB

GND

GND

SS

VIN

VSUP

LX

LX

EN

9

8

7

1

2

3

4

5

10

6

11

R4

C2

GND

GND

L1

D1

GND

R1

R2

to VIN as possible.

Place the power components as

close to the IC as possible. The

traces should be wide and short,

especially for the high-current loop.

The compensation circuit

should be kept away from the

power loops and should be

shielded with a ground trace to

prevent any noise coupling.

The feedback voltage-divider

resistors must be near the

feedback pin. The divider center

trace must be shorter and avoid the

trace near any switching nodes.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0

25

50

75

100

125

Ambient Temperature (°C)

Four Layer PCB