IDT77V1254L25 datasheet(6/47 Pages) IDT

Part #	IDT77V1254L25

Description	Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks

Download	47 Pages

Scroll/Zoom	100%

Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

Logo

6 / 47 page

6 of 47

September 21, 2001

IDT77V1254L25

TXLED[3:0]

12, 13, 14, 15

Out

Ports 3 thru 0 Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when this port

receives a cell for transmission. 8 mA drive current both high and low. One per port.

TXREF

10

In

Transmit Reference. Synchronous to OSC. On the falling edge, an X_8 command byte is inserted into the

transmit data stream. Logic for this signal is programmed in register 0x40. Typical application is WAN timing.

Power Supply Signals

Signal Name

Pin Number

I/O

Signal Description

AGND

112, 117, 118, 123, 124,

127, 129, 130, 135, 136, 141

____

Analog ground. AGND supply a ground reference to the analog portion of the ship, which sources a more

constant current than the digital portion.

AVDD

113, 116, 119, 122, 125,

128, 131, 134, 137, 140

____

Analog power supply 3.3 ± 0.3V AVDD supply power to the analog portion of the chip, which draws a more

constant current than the digital portion.

GND

2, 11, 44, 50, 56, 67, 77, 83,

86, 97, 107, 111, 142

____

Digital Ground.

VDD

1, 5, 16, 38, 45, 57, 68, 78,

84, 92, 104, 108

____

Digital power supply. 3.3 ± 0.3V.

16-BIT UTOPIA 2 Signals (MODE[1:0] = 00)

Signal Name

Pin Number

I/O

Signal Description

RXADDR[4:0] 53, 52, 51, 49, 48

In

Utopia 2 Receive Address Bus. This bus is used in polling and selecting the receive port. The port addresses

are defined in bits [4:0] of the Enhanced Control Registers.

RXCLAV

54

Out

Utopia 2 Receive Cell Available. Indicates the cell available status of the addressed port. It is asserted when

a full cell is available for retrieval from the receive FIFO. When non of the four ports is addressed. RXCLAV is

high impedance.

RXCLK

46

In

Utopia 2 Receive Clock. This is a free running clock input.

RXDATA[15:0] 59, 60, 61, 62, 63, 64, 65,

66, 69, 70, 71, 72, 73, 74,

75, 76

Out

Utopia 2 Receive Data. When one of the four ports is selected, the 77V1254L25 transfers received cells to an

ATM device across this bus. Also see RXPARITY.

RXEN

47

In

Utopia 2 Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA

bus.

RXPARITY

58

Out

Utopia 2 Receive Data Parity. Odd parity over RXDATA[15:0].

RXSOC

55

Out

Utopia 2 Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.

TXADDR[4:0] 36, 37, 39, 40, 41

In

Utopia 2 Transmit Address Bus. This bus is used in polling and selecting the transmit port. The port

addresses are defined in bits [4:0] of the Enhanced Control Registers.

TXCLAV

42

Out

Utopia 2 Transmit Cell Available. Indicates the availability of room in the transmit FIFO of the addressed port

for a full cell. When none of the four ports is addressed, TXCLAV is high impedance.

TXCLK

43

In

Utopia Transmit Clock. This is a free running clock input.

TXDATA[15:0] 32, 31, 30, 29, 28, 27, 26,

25, 24, 23, 22, 21, 20, 19,

18, 17

In

Utopia 2 Transmit Data. An ATM device transfers cells across this bus to the 77V1254L25 for transmission.

Also see TXPARITY.

TXEN

34

In

Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA

bus.

TXPARITY

33

In

Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0]. Parity is checked and errors are indicated in

the Interrupt Status Registers, as enabled in the Master Control Registers. No other action is taken in the

event of an error. Tie high or low if unused.

TXSOC

35

In

Utopia 2 Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.

Table 1 Signal Descriptions (Part 2 of 3)

Similar Part No. - IDT77V1254L25

Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDT77V1253	449Kb / 44P	TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS
Integrated Device Techn...	IDT77V1253L25PGI	449Kb / 44P	TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS

More results

Similar Description - IDT77V1254L25

Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDT77V1253	449Kb / 44P	TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS
	IDT77V1264L200	390Kb / 49P	Quad Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications
	IDT77V126L200	229Kb / 30P	Single Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications
	IDT77V106L25	216Kb / 27P	3.3V ATM PHY for 25.6 and 51.2 Mbps
	IDT77105	335Kb / 24P	PHY (TC-PMD) for 25.6 Mbps ATM Networks
	IDT77V107	325Kb / 24P	Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2
PMC-Sierra, Inc	PM5358	39Kb / 2P	Quad Channel OC-12c ATM and POS Physical Layer Device
	PM5349	72Kb / 4P	Quad 155 Mb/s ATM Physical Layer Device
	PM5349-1	60Kb / 2P	Quad 155 Mb/s ATM Physical Layer Device
	PM7375	1Mb / 430P	LOCAL ATM SAR & PHYSICAL LAYER

More results

IDT77V1254L25 Datasheet(PDF) 6 Page - Integrated Device Technology

IDT77V1254L25 Datasheet(HTML) 6 Page - Integrated Device Technology

Similar Part No. - IDT77V1254L25

Similar Description - IDT77V1254L25

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL