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UP9305WSU8 Datasheet(PDF) 9 Page - uPI Group Inc. |
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UP9305WSU8 Datasheet(HTML) 9 Page - uPI Group Inc. |
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9 / 16 page  uP9305 9 uP9305-DS-C3000, Aug. 2015 www.upi-semi.com Conceptual Application Information Component Selection Guidelines The selection of external component is primarily determined by the maximum load current and begins with the selection of power MOSFET switches. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, C IN is selected for its capability to handle the large RMS current into the converter and C OUT is chosen with low enough ESR to meet the output voltage ripple and transient specification. Power MOSFET Selection The uP9305 requires two external N-channel power MOSFETs for upper (controlled) and lower (synchronous) switches. Important parameters for the power MOSFETs are the breakdown voltage V (BR)DSS, on-resistance RDS(ON), reverse transfer capacitance C RSS, maximum current IDS(MAX), gate supply requirements, and thermal management requirements. The gate drive voltage is supplied by VCC pin that receives 4.5V~13.2V supply voltage. When operating with a 7~13.2V power supply for VCC, a wide variety of NMOSFETs can be used. Logic-level threshold MOSFET should be used if the input voltage is expected to drop below 7V. Caution should be exercised with devices exhibiting very low V GS(ON) characteristics. The shoot-through protection present aboard the uP9305 may be circumvented by these MOSFETs if they have large parasitic impedances and/or capacitances that would inhibit the gate of the MOSFET from being discharged below its threshold level before the complementary MOSFET is turned on. Also avoid MOSFETs with excessive switching times; the circuitry is expecting transitions to occur in under 30ns or so. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components: conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty cycle. Since the uP9305 is operating in continuous conduction mode, the duty cycles for the MOSFETs are: IN OUT UP V V D = ; IN OUT IN LOW V V V D − = The resulting power dissipation in the MOSFETs at maximum output current are: OSC SW IN OUT UP ) ON ( DS 2 OUT UP f T V I 5 . 0 D R I P × × × × + × × = LOW ) ON ( DS 2 OUT LOW D R I P × × = where T SW is the combined switch ON and OFF time. Both MOSFETs have I2R losses and the upper MOSFET includes an additional term for switching losses, which are largest at high input voltages. The lower MOSFET losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. These equations assume linear voltage current transitions and do not adequately model power loss due the reverse-recovery of the lower MOSFET’s body diode. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. The gate-charge losses are mainly dissipated by the uP9305 and don’t heat the MOSFETs. However, large gate charge increases the switching interval, T SW that increases the MOSFET switching losses. The gate-charge losses are calculated as: OSC UP _ RSS IN LO _ ISS UP _ ISS CC CC C _ G f ) C V ) C C ( V ( V P × × + + × × = where C ISS_UP is the input capacitance of the upper MOSFET, C ISS_LOW is the input capacitance of the lower MOSFET, and C RSS_UP is the reverse transfer capacitance of the upper MOSFET. Make sure that the gate-charge loss will not cause over temperature at uP9305, especially with large gate capacitance and high supply voltage. Output Inductor Selection Output inductor selection usually is based on the considerations of inductance, rated current, size requirements and DC resistance (DCR). Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ) V V 1 ( V L f 1 I IN OUT OUT OUT OSC L − × = ∆ Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 20% of I OUT(MAX). There is another tradeoff between output ripple current/ voltage and response time to a transient load. Increasing the value of inductance reduces the output ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. |
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