uP9305

4

uP9305-DS-C3000, Aug. 2015

www.upi-semi.com

Conceptual

The uP9305 is a compact synchronous-rectified buck

controller specifically designed to operate from 5V or 12V

supply voltage and to deliver high quality output voltage as

low as 0.6V.

Supply Voltage

The VCC pin receives a well-decoupled 4.5V to 13.2V

supply voltage to power the control circuit, the lower gate

driver and the bootstrap circuit for the higher gate driver. A

minimum 1uF ceramic capacitor is recommended to bypass

the supply voltage. Place the bypassing capacitor physically

near the IC.

An internal linear regulator regulates the supply voltage

into a 4.2V voltage VDD for internal control logic circuit. No

external bypass capacitor is required for filtering the VDD

voltage.

The uP9305 integrates MOSFET gate drives that are

powered from the VCC pin and support 12V+12V driving

capability. A bootstrap diode is embedded to facilitate PCB

design and reduce the total BOM cost. No external

Schottky diode is required. Converters that consist of

uP9305 feature high efficiency without special consideration

on the selection of MOSFETs.

Note: The embedded bootstrap diode is not a Schottky

diode having a 0.8V forward voltage. External

Schottky diode is highly recommended if the VCC

voltage is expected to be lower than 5.0V. Otherwise

the bootstrap diode may be too low for the device to

work normally.

Power On Reset and Chip Enable

A power on reset (POR) circuitry continuously monitors

the supply voltage at VCC pin. Once the rising POR

threshold is exceeded, the uP9305 sets itself to active

state and is ready to accept chip enable command. The

rising POR threshold is typically 4.2V at VCC rising.

The COMP/EN is a multifunctional pin: control loop

compensation and chip enable as shown in Figure 1. An

Enable Comparator monitors the COMP/EN pin voltage for

chip enable. A signal level transistor is adequate to pull

this pin down to ground and shut down the uP9305. An

80uA current source charges the external compensation

network with 1.0V ceiling when this pin is released. If the

voltage at COMP/EN pin exceeds 0.3V, the uP9305

initiates its softstart cycle.

The 80uA current source keeps charging the COMP pin to

its ceiling until the feedback loop boosts the COMP pin

higher than 0.8V according to the feedback signal. The

current source is cut off when V

during normal operation.

FB

Enable

Disable

COMP/EN

0.3V

1V

Chip

Enable

Error

Amplifier

uP9305

Figure 1. Chip Enable Function

Soft Start

A built-in Soft Start is used to prevent surge current from

power supply input during turn on (referring to the Functional

Block Diagram). The error amplifier is a three-input device.

Reference voltage V

whichever is smaller dominates the behavior of the non-

inverting inputs of the error amplifier. SS internally ramps

up to VCC and the output voltage will follow the SS signal

and ramp up smoothly to its target level.

The SS signal keeps ramping up after it exceeds the

reference voltage V

takes over the behavior of error amplifier after SS > V

When the SS signal climb to 1.3 x V

the end of softstart cycle and enables the over and under

voltage protection of the output voltage.

Figure 2 shows a typical start up interval for uP9305 where

the COMP/SD pin has been released from a grounded

(system shutdown) state.

The internal 80uA current source starts to charge the

compensation network after the COMP/SD pin is released

from grounded at T1. The COMP/SD exceeds 0.3V and

enables the uP9305 at T2. The COMP/SD continues

ramping up and stays at 1V before the SS starts ramping

up at T3. The uP9305 initializes itself such as current limit

level setting (see the relative section) during the time interval

between T2 and T3. The output voltage follows the internal

SS and ramps up to its final level during T3 and T4. At T4,

the reference voltage V

error amplifier as the internal SS crosses V

SS keeps ramping up and reaches 1.3 x V

the uP9305 asserts the end of softstart cycle.

Functional Description