IDT723623 datasheet(14/28 Pages) JGD

Part #	IDT723623

Description	CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36

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Manufacturer	JGD [Jinan Gude Electronic Device]

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COMMERCIALTEMPERATURERANGE

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™

256 x 36, 512 x 36, 1,024 x 36

HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35. For

an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this case,

B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are

placed on B0-B8. (In this case, B9-B35 are indeterminate.)

TheMail2RegisterFlag(

MBF2)issetHIGHbyaLOW-to-HIGHtransition

on CLKA when a Port A read is selected by

CSA, W/RA, and ENA with MBA

HIGH.

For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For

an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,

A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are

placed on A0-A8. (In this case, A9-A35 are indeterminate.)

The data in a mail register remains intact after it is read and changes only

whennewdataiswrittentotheregister. TheEndianSelectfeaturehasnoeffect

on mailbox data. For mail register and mail register flag timing diagrams, see

Figure 17 and 18.

BUS SIZING

The Port B bus can be configured in a 36-bit long word, 18-bit word, or

9-bit byte format for data read from the FIFO. The levels applied to the Port B

Bus Size Select (SIZE) and the Bus-Match Select (BM) determine the Port B

bus size. These levels should be static throughout FIFO operation. Both bus

sizeselectionsareimplementedatthecompletionofReset,bythetimetheFull/

Input Ready flag is set HIGH, as shown in Figure 2.

TwodifferentmethodsforsequencingdatatransferareavailableforPort

B when the bus size selection is either byte-or word-size. They are referred

to as Big-Endian (most significant byte first) and Little-Endian (least significant

bytefirst). ThelevelappliedtotheBig-EndianSelect(BE)inputduringtheLOW-

to-HIGH transition of

RS1selectstheendianmethodthatwillbeactiveduring

FIFO operation. BE is a don’t care input when the bus size selected for Port B

islongword.TheendianmethodisimplementedatthecompletionofReset,by

the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.

Only 36-bit long word data is written to or read from the FIFO memory

on the IDT723623/723633/723643. Bus-matching operations are done after

data is read from the FIFO RAM. These bus-matching operations are not

available when transferring data via mailbox registers. Furthermore, both the

word-andbyte-sizebusselectionslimitthewidthofthedatabusthatcanbeused

for mail register operations. In this case, only those byte lanes belonging to the

selected word- or byte-size bus can carry mailbox data. The remaining data

outputswillbeindeterminate.Theremainingdatainputswillbedon’tcareinputs.

For example, when a word-size bus is selected, then mailbox data can be

transmitted only between A0-A17 and B0-B17. When a byte-size bus is

selected, then mailbox data can be transmitted only between A0-A8 and B0-

B8. (See Figures 17 and 18).

BUS-MATCHING FIFO READS

Data is read from the FIFO RAM in 36-bit long word increments. If a long

wordbussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFO

output register. If byte or word size is implemented on Port B, only the first one

ortwobytesappearontheselectedportionoftheFIFOoutputregister,withthe

restofthelongwordstoredinauxiliaryregisters. Inthiscase,subsequentFIFO

reads output the rest of the long word to the FIFO output register in the order

shown by Figure 2.

When reading data from FIFO in byte or word format, the unused B0-B35

outputsareindeterminate.

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