 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT723623 Datasheet(PDF) 13 Page - Jinan Gude Electronic Device |
|
|
|||||||||||||||||||||||||||||
IDT723623 Datasheet(HTML) 13 Page - Jinan Gude Electronic Device |
|
|
13 / 28 page  13 COMMERCIALTEMPERATURERANGE IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW if a word in memory is the next data to be sent to the FlFO output register and twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing the Empty Flag HIGH; only then can data be read. ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs at time tSKEW1or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 10 and 11). FULL/INPUT READY FLAGS ( FF/IR) This is a dual purpose flag. In FWFT mode, the Input Ready (IR) function is selected. In IDT Standard mode, the Full Flag ( FF) functionisselected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the FIFO to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored. The Full/Input Ready flag of a FlFO is synchronized to the port clock that writes data to its array (CLKA). For both FWFT and IDT Standard modes, each timeawordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine that controls a Full/Input Ready flag monitors a write pointer and read pointer comparator that indicates when the FlFO memory status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizingclock. Therefore,anFull/InputReadyflagisLOWiflessthantwo cycles of the Full/Input Ready flag synchronizing clock have elapsed since the nextmemorywritelocationhasbeenread. ThesecondLOW-to-HIGHtransition ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input Ready flag HIGH. A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursattime tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 13 and 14). ALMOST-EMPTY FLAG ( AE) TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads datafromitsarray(CLKB).ThestatemachinethatcontrolsanAlmost-Emptyflag monitors a write pointer and read pointer comparator that indicates when the FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.The Almost-EmptystateisdefinedbythecontentsofregisterX.Theseregistersare loaded with preset values during a FIFO reset, programmed from Port A, or programmedserially(seeAlmost-EmptyflagandAlmost-Fullflagoffsetprogram- ming section). An Almost-Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. Note that a data word present in the FIFO output register has been read from memory. TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock are required after a FIFO write for its Almost-Empty flag to reflect the new level offill.Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormorewords remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe writethatfilledthememorytothe(X+1)level.AnAlmost-EmptyflagissetHIGH bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO writethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionofanAlmost- Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchro- nization cycle. (See Figure 15). ALMOST-FULL FLAG ( AF) The Almost-Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost-Full flag monitors a writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory statusisalmost-full,almost-full-1,oralmost-full-2.TheAlmost-Fullstateisdefined by the contents of register Y. These registers are loaded with preset values during a FlFO reset or, programmed from Port A, or programmed serially (see Almost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection). AnAlmost- Full flag is LOW when the number of words in its FIFO is greater than or equal to(256-Y),(512-Y),or(1,024-Y)fortheIDT723623,IDT723633,orIDT723643 respectively. AnAlmost-FullflagisHIGHwhenthenumberofwordsinitsFIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723623, IDT723633, or IDT723643 respectively. Note that a data word present in the FIFO output register has been read from memory. TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock are required after a FIFO read for its Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [256/ 512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber ofwordsinmemoryto[256/512/1,024-(Y+1)]. ALOW-to-HIGHtransitionofan Almost-Full flag synchronizing clock begins the first synchronization cycle if it occursattimetSKEW2 orgreaterafterthereadthatreducesthenumberofwords inmemoryto[256/512/1024-(Y+1)]. Otherwise,thesubsequentsynchronizing clock cycle may be the first synchronization cycle. (See Figure 16). MAILBOX REGISTERS Two 36-bit bypass registers are on the IDT723623/723633/723643 to passcommandandcontrolinformationbetweenPortAandPortBwithoutputting it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usable width of both the Mail1 and Mail2 registers matches the selected bus size for Port B. ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen aPortAwriteisselectedby CSA,W/RA,andENAwithMBAHIGH. Iftheselected Port B bus size is 36 bits, the usable width of the Mail1 register employs data lines A0-A35. If the selected Port B bus size is 18 bits, then the usable width of the Mail1 Register employs data lines A0-A17. (In this case, A18-A35 are don’t care inputs.) If the selected Port B bus size is 9 bits, then the usable width of the Mail1 Register employs data lines A0-A8. (In this case, A9-A35 are don’t care inputs.) A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2 Register when a Port B write is selected by CSB, W/RB, and ENB with MBB HIGH. If the selected Port B bus size is 36 bits, the usable width of the Mail2 employs data lines B0-B35. If the selected Port B bus size is 18 bits, then the usablewidthoftheMail2RegisteremploysdatalinesB0-B17. (Inthiscase,B18- B35aredon’tcareinputs.) IftheselectedPortBbussizeis9bits,thentheusable widthoftheMail2RegisteremploysdatalinesB0-B8. (Inthiscase,B9-B35are don’t care inputs.) Writingdatatoamailregistersetsitscorrespondingflag( MBF1orMBF2) LOW. AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW. Whendataoutputsofaportareactive,thedataonthebuscomesfromthe FIFO output register when the port Mailbox Select input is LOW and from the mail register when the port Mailbox Select input is HIGH. TheMail1RegisterFlag( MBF1)issetHIGHbyaLOW-to-HIGHtransition on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB |
Similar Part No. - IDT723623 |
|
Similar Description - IDT723623 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
