10

COMMERCIALTEMPERATURERANGE

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™

256 x 36, 512 x 36, 1,024 x 36

A HIGH on the BE/

FWFT input when the Reset (RS1) input goes from

LOW to HIGH will select a Big-Endian arrangement. In this case, the most

significant byte (word) of the long word written to Port A will be read from Port

B first; the least significant byte (word) of the long word written to Port A will be

read from Port B last.

ALOWontheBE/

FWFTinputwhentheReset(RS1)inputgoesfromLOW

toHIGHwillselectaLittle-Endianarrangement. Inthiscase,theleastsignificant

byte (word) of the long word written to Port A will be read from Port B first; the

most significant byte (word) of the long word written to Port A will be read from

Port B last. Refer to Figure 2 for an illustration of the BE function. See Figure

3 (Reset) for an Endian select timing diagram.

— TIMING MODE SELECTION

AfterReset, theFWFTselectfunctionisactive,permittingachoicebetween

two possible timing modes: IDT Standard mode or First Word Fall Through

(FWFT) mode. Once the Reset (

RS1)inputisHIGH,aHIGHontheBE/FWFT

inputduringthenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectIDT

Standard mode. This mode uses the Empty Flag function (

EF) to indicate

whether or not there are any words present in the FIFO memory. It uses the

FullFlagfunction(

FF)toindicatewhetherornottheFIFOmemoryhasanyfree

space for writing. In IDT Standard mode, every word read from the FIFO,

including the first, must be requested using a formal read operation.

OncetheReset(

RS1)inputisHIGH,aLOWontheBE/FWFTinputduring

the next LOW-to-HIGH transition of CLKA and CLKB will select FWFT mode.

ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere

is valid data at the data outputs (B0-B35). It also uses the Input Ready function

(IR) to indicate whether or not the FIFO memory has any free space for writing.

In the FWFT mode, the first word written to an empty FIFO goes directly to data

outputs, no read request necessary. Subsequent words must be accessed by

performing a formal read operation.

Following Reset, the level applied to the BE/

FWFT input to choose the

desired timing mode must remain static throughout FIFO operation. Refer to

Figure 3 (Reset) for a First Word Fall Through select timing diagram.

PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS

Two registers in the IDT723623/723633/723643 are used to hold the

offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags. TheAlmost-Emptyflag

(

AE)OffsetregisterislabeledXandAlmost-Fullflag(AF)Offsetregisterislabeled

Y. The offset registers can be loaded with preset values during the reset of the

FIFO, programmed in parallel using the FIFO’s Port A data inputs, or

programmedinserialusingtheSerialData(SD)input(seeTable1).

SPM,FS0/

SD and FS1/

SEN function the same way in both IDT Standard and FWFT

modes.

— PRESET VALUES

To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers

with one of the three preset values listed in Table 1, the Serial Program Mode

(

SPM)andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-

to-HIGH transition of the Reset input (

RS1). For example, to load the preset

value of 64 into X and Y,

SPM,FS0andFS1mustbeHIGHwhenRS1returns

HIGH. For the relevant preset value loading timing diagram, see Figure 3.

SIGNAL DESCRIPTION

RESET (

RS1/RS2)

Afterpowerup,aResetoperationmustbeperformedbyprovidingaLOW

pulse to

RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the

IDT723623/723633/723643 undergoes a complete reset by taking its Reset

(

RS1 and RS2) input LOW for at least four Port A clock (CLKA) and four Port

B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch

asynchronously to the clocks. A Reset initializes the internal read and write

pointers and forces the Full/Input Ready flag (

FF/IR)LOW,theEmpty/Output

Ready flag (

EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-

Full flag (

AF)HIGH. AReset(RS1)alsoforcestheMailboxflag(MBF1)ofthe

parallelmailboxregisterHIGH,andatthesametimethe

RS2andMBF2operate

likewise. After a Reset, the FIFO’s Full/Input Ready flag is set HIGH after two

write clock cycles to begin normal operation.

ALOW-to-HIGHtransitionontheFlFOReset(

RS1)inputlatchesthevalue

of the Big-Endian (BE) input for determining the order by which bytes are

transferred through Port B.

ALOW-to-HIGHtransitionontheFlFOReset(

RS1)inputalsolatchesthe

values of the Flag Select (FS0, FS1) and Serial Programming Mode (

SPM)

inputs for choosing the Almost-Full and Almost-Empty offset programming

method (for details see Table 1, Flag Programming, and Almost-Empty and

Almost-Fullflagoffsetprogramming section).TherelevantReset timingdiagram

can be found in Figure 3.

PARTIAL RESET (

PRS)

The FIFO memory of the IDT723623/723633/723643 undergoes a

limited reset by taking its associated Partial Reset (

PRS)inputLOWforatleast

fourPortAclock(CLKA)andfourPortBclock(CLKB)LOW-to-HIGHtransitions.

ThePartialResetinput canswitchasynchronouslytotheclocks. APartialReset

initializes the internal read and write pointers and forces the Full/Input Ready

flag (

FF/IR) LOW, the Empty/Output Ready flag (EF/OR) LOW, the Almost-

Emptyflag(

AE)LOW,andtheAlmost-Fullflag(AF)HIGH. APartialResetalso

forces the Mailbox flag (

MBF1, MBF2) of the parallel mailbox register HIGH.

AfteraPartialReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoclock

cycles to begin normal operation. See Figure 4, Partial Reset (IDTStandard

and FWFT Modes) for the relevant timing diagram.

Whateverflagoffsets,programmingmethod(parallelorserial),andtiming

mode(FWFTorIDTStandardmode)arecurrentlyselectedat thetimeaPartial

Reset is initiated, those settings will be remain unchanged upon completion of

the reset operation. A Partial Reset may be useful in the case where

reprogramming a FIFO following a Reset would be inconvenient.

BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/

FWFT)

— ENDIAN SELECTION

This is a dual purpose pin. At the time of Reset, the BE select function is

active,permittingachoiceofBig-orLittle-Endianbytearrangementfordataread

from Port B. This selection determines the order by which bytes (or words) of

dataaretransferredthroughthisport. Forthefollowingillustrations,assumethat

a byte (or word) bus size has been selected for Port B. (Note that when Port

B is configured for a long word size, the Big-Endian function has no application

NOTE:

1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused

inputs) must not be left open, rather they must be either HIGH or LOW.