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IDT723623 Datasheet(PDF) 8 Page - Jinan Gude Electronic Device |
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IDT723623 Datasheet(HTML) 8 Page - Jinan Gude Electronic Device |
8 / 28 page 8 COMMERCIALTEMPERATURERANGE IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 Symbol Parameter Min. Max. Min. Max. Unit fS Clock Frequency, CLKA or CLKB — 83 — 66.7 MHz tCLK Clock Cycle Time, CLKA or CLKB 12 — 15 — ns tCLKH Pulse Duration, CLKA or CLKB HIGH 5 — 6 — ns tCLKL Pulse Duration, CLKA and CLKB LOW 5 — 6 ns tDS Setup Time, A0-A35 before CLKA ↑ and B0-B35 before CLKB↑ 3— 4 ns tENS1 Setup Time, CSA and W/RA before CLKA ↑; CSB and W/RB before CLKB↑ 4 — 4.5 — ns tENS2 Setup Time, ENA and MBA before CLKA ↑; ENB and MBB before CLKB↑ 3 — 4.5 — ns tRSTS Setup Time, RS1 or PRS LOW before CLKA ↑ or CLKB↑(2) 5 — 5 — ns tFSS Setup Time, FS0 and FS1 before RS1 HIGH 7.5 — 7.5 — ns tBES Setup Time, BE/ FWFT before RS1 HIGH 7.5 — 7.5 — ns tSPMS Setup Time, SPM before RS1 HIGH 7.5 — 7.5 — ns tSDS Setup Time, FS0/SD before CLKA ↑ 3 — 4 — ns tSENS Setup Time, FS1/ SEN before CLKA ↑ 3 — 4 — ns tFWS Setup Time, FWFT before CLKA ↑ 0 — 0 — ns tDH Hold Time, A0-A35 after CLKA ↑and B0-B35 after CLKB↑ 0.5 — 1 — ns tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA ↑; CSB, W/RB,ENB, and MBB after CLKB↑ 0.5 — 1 — ns tRSTH Hold Time, RS1 or PRS LOW after CLKA ↑ or CLKB↑(2) 4 — 4 — ns tFSH Hold Time, FS0 and FS1 after RS1 HIGH 2 — 2 — ns tBEH Hold Time, BE/FWFT after RS1 HIGH 2 — 2 — ns tSPMH Hold Time, SPM after RS1 HIGH 2 — 2 — ns tSDH Hold Time, FS0/SD after CLKA ↑ 0.5 — 1 — ns tSENH Hold Time, FS1/ SEN HIGH after CLKA ↑ 0.5 — 1 — ns tSPH Hold Time, FS1/ SEN HIGH after RS1 HIGH 2 — 2 — ns tSKEW1(3) Skew Time between CLKA ↑ and CLKB↑ for EF/OR and FF/IR 5 — 7.5 — ns tSKEW2(3,4) Skew Time between CLKA ↑ and CLKB↑ for AE and AF 12 — 12 — ns TIMING REQUIREMENTS OVER RECOMMENDED RANGES O. SUPPLY VOLTAGE AND OPERATING .REE-AIR TEMPERATURE NOTES: 1. Industrial temperature range is available by special order. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 4. Design simulated, not tested. (Commercial: VCC = 5.0V ± 10%, TA = 0 °C to +70°C) Commercial IDT723623L12 IDT723623L15 IDT723633L12 IDT723633L15 IDT723643L12 IDT723643L15 |
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