IDT723623 datasheet(7/28 Pages) JGD

Part #	IDT723623

Description	CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36

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Manufacturer	JGD [Jinan Gude Electronic Device]

Direct Link	http://www.jgd.com.cn

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COMMERCIALTEMPERATURERANGE

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™

256 x 36, 512 x 36, 1,024 x 36

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723623/723633/723643 with CLKA

andCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnected

to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of IDT723623/723633/723643 inputs

driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.

CALCULATING POWER DISSIPATION

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

PT = VCC x [ICC(f) + (N x

∆ICC x dc)] + Σ(CL x VCC2 X fo)

where:

N

=

number of used outputs = 36-bit (long word), 18-bit (word) or 9-bit (byte) bus size

∆ICC

=

increase in power supply current for each input at a TTL HIGH level

dc

=

duty cycle of inputs at a TTL HIGH level of 3.4 V

CL

=

outputcapacitanceload

fo

=

switching frequency of an output

Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)

010

20

30

40

50

60

70

0

50

100

250

300

VCC = 5.0V

fS

 Clock Frequency  MHz

fdata = 1/2 fS

TA = 25

°C

CL = 0pF

VCC = 5.5V

3269 drw 02a

200

150

VCC = 4.5V

80

90

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