26

COMMERCIALTEMPERATURERANGE

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™

256 x 36, 512 x 36, 1,024 x 36

Figure 18. Timing for Mail2 Register and

NOTE:

1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data (A18-A35 will

be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don't care inputs). In this second case, A0-A8 will have valid

data (A9-A35 will be indeterminate).

Figure 19. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with

Programmable Flags used in Depth Expansion Configuration

NOTES:

1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)

2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.

3. The amount of time it takes for

EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO

4. The amount of time it takes for

FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:

•

DATA IN (Dn)

READ CLOCK (CLKB)

READ ENABLE (ENB)

EMPTY FLAG/

OUTPUT READY (

EF/OR)

CHIP SELECT (

CSB)

DATA OUT (Qn)

TRANSFER CLOCK

3269 drw20

IDT

723623

723633

723643

IDT

723623

723633

723643

WRITE

READ

MBA

CHIP SELECT (

CSA)

WRITE SELECT (W/

RA)

WRITE ENABLE (ENA)

ALMOST-FULL FLAG (

AF)

FULL FLAG/

INPUT READY (

FF/IR)

WRITE CLOCK (CLKA)

CLKB

EF/OR

ENB

CSB

W/RB

MBB

CLKA

ENA

FF/IR

CSA

MBA

W/

RA

READ SELECT (

W/RB)

ALMOST-EMPTY FLAG (

AE)

MBB

n

n

n

Qn

Dn

3269 drw19

CLKB

ENB

B0-B35

MBB

CSB

W/RB

CLKA

MBF2

CSA

MBA

ENA

A0-A35

W/

RA

FIFO Output Register

W1 (Remains valid in Mail2 Register after read)

W1