24

COMMERCIALTEMPERATURERANGE

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™

256 x 36, 512 x 36, 1,024 x 36

NOTES:

FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge

FF may transition HIGH one CLKA cycle later than shown.

Figure 14.

NOTES:

AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge

AE may transition HIGH one CLKB cycle later than shown.

2. FIFO Write (

CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.

3. If Port B size is word or byte,

AE is set LOW by the last word or byte read from the FIFO, respectively.

Figure 15. Timing for

AE

CLKA

ENB

3269 drw16

ENA

CLKB

2

1

X Word in FIFO

(X+1) Words in FIFO

CSB

EF

W/RB

MBB

ENB

B0-B35

CLKB

FF

CLKA

CSA

3269 drw15

W/

RA

A0-A35

MBA

ENA

12

To FIFO

Previous Word in FIFO Output Register

Next Word From FIFO

LOW

HIGH

LOW

HIGH

LOW

HIGH

(1)

FIFO Full

WFF

WFF

t

t