17

COMMERCIALTEMPERATURERANGE

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™

256 x 36, 512 x 36, 1,024 x 36

Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)

NOTE:

1.

CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.

Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset. (IDT Standard and FWFT Modes)

NOTES:

1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until

FF/IR is set HIGH.

2. Programmable offsets are written serially to the SD input in the order

AF offset (Y) and AE offset (X).

CLKA

FF/IR

FS1/

SEN

AE Offset

(X) LSB

AF Offset

(Y) MSB

RS1

4

SPM

3269 drw07

3269 drw06

CLKA

RS1

FF/IR

A0-A35

FS1,FS0

ENA

4

0,0

AF Offset

(Y)

AE Offset

(X)

First Word to FIFO

SPM

1

2