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70V657S12DRGI8 Datasheet(PDF) 12 Page - Integrated Device Technology |
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70V657S12DRGI8 Datasheet(HTML) 12 Page - Integrated Device Technology |
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12 / 24 page  IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 12 Timing of Power-Up Power-Down Waveform of Read Cycles(5) NOTES: 1. Timing depends on which signal is asserted last, OE, CE or BEn. 2. Timing depends on which signal is de-asserted first CE, OE or BEn. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. tRC R/ W CE ADDR tAA OE BEn 4869 drw 06 (4) tACE (4) tAOE (4) tABE (4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATAOUT BUSYOUT VALID DATA (4) . CE 4869 drw 07 tPU ICC ISB tPD 50% 50% . |
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