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70V657S12DRGI8 Datasheet(PDF) 20 Page - Integrated Device Technology |
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70V657S12DRGI8 Datasheet(HTML) 20 Page - Integrated Device Technology |
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20 / 24 page  IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 20 Busy Logic BusyLogicprovidesahardwareindicationthatbothportsoftheRAM haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”. TheBUSY pincanthenbeusedtostalltheaccessuntiltheoperationon theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally to prevent the write from proceeding. TheuseofBUSYlogicisnotrequiredordesirableforallapplications. InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether and use any BUSY indication as an interrupt source to flag the event of anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT70V659/58/57 RAM in master mode, arepush-pulltypeoutputsanddonotrequirepullupresistorstooperate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit decisioncouldresultwithonemasterindicatingBUSYononesideofthe array and another master indicating BUSY on one other side of thearray.Thiswouldinhibitthewriteoperationsfromoneportforpartof awordandinhibitthewriteoperationsfromtheotherportforthe otherpart of the word. The BUSY arbitration on a master is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enoughforaBUSYflagtobeoutputfromthemasterbeforethe actualwrite pulsecanbeinitiatedwiththeR/Wsignal.Failureto observethistiming canresultinaglitchedinternalwriteinhibitsignalandcorrupteddatainthe slave. Semaphores The IDT70V659/58/57 is an extremely fast Dual-Port 128/64/32K x 36CMOSStaticRAMwithanadditional8addresslocationsdedicatedto binarysemaphoreflags.Theseflagsalloweitherprocessorontheleftor right sideoftheDual-PortRAMtoclaimaprivilegeovertheotherprocessor forfunctionsdefinedbythesystemdesigner’ssoftware.Asanexample, the semaphore can be used by one processor to inhibit the other from accessingaportionoftheDual-PortRAMoranyothersharedresource. TheDual-PortRAMfeaturesafastaccesstime,withbothportsbeing completelyindependentofeachother.Thismeansthatthe activityonthe left port in no way slows the access time of the right port. Both ports are identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom orwrittentoatthesametimewiththeonlypossibleconflictarisingfromthe simultaneous writing of, or a simultaneous READ/WRITE of, a non- semaphorelocation.Semaphoresareprotectedagainstsuchambiguous situationsandmaybeusedbythesystemprogramtoavoidanyconflicts inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol on-chip power down circuitry that permits the respective port to go into standbymodewhennotselected. SystemswhichcanbestusetheIDT70V659/58/57containmultiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems canbenefitfromaperformanceincreaseofferedbytheIDT70V659/58/ 57shardwaresemaphores,whichprovidealockoutmechanismwithout requiringcomplexprogramming. Software handshaking between processors offers the maximum in systemflexibilitybypermittingsharedresourcestobeallocatedinvarying configurations. The IDT70V659/58/57 does not use its semaphore flagstocontrolanyresourcesthroughhardware,thusallowingthesystem designertotalflexibilityinsystemarchitecture. An advantage of using semaphores rather than the more common methodsofhardwarearbitrationisthatwaitstatesareneverincurredin either processor. This can prove to be a major advantage in very high- speedsystems. 4869 drw 18 MASTER Dual Port RAM BUSYR CE0 MASTER Dual Port RAM BUSYR SLAVE Dual Port RAM BUSYR SLAVE Dual Port RAM BUSYR CE1 CE1 CE0 A17(1,2) BUSYL BUSYL BUSYL BUSYL . a"don'tcare".Likewise,therightportinterruptflag(INTR)isassertedwhen theleftportwritestomemorylocation1FFFF(HEX)(FFFFforIDT70V658 and7FFFforIDT70V657)andtocleartheinterruptflag(INTR),theright port must read the memory location 1FFFF (FFFF for IDT70V658 and 7FFF for IDT70V657). The message (36 bits) at 1FFFE (FFFE for IDT70V658 and 7FFE for IDT70V657)or 1FFFF (FFFF for IDT70V658 and 7FFF for IDT70V657) is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFFE (FFFE for IDT70V658 and 7FFE for IDT70V657) and 1FFFF (FFFF for IDT70V658 and 7FFF for IDT70V657) are not used as mail boxes,butaspartoftherandomaccessmemory.RefertoTruthTableIII fortheinterruptoperation. Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT70V659/58/57 RAM array in width while usingBUSYlogic,onemasterpartisusedtodecidewhichsideoftheRAMs array will receive a BUSY indication, and to output that indication. Any Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V659/58/57 RAMs. numberofslavestobeaddressedinthesameaddressrangeasthemaster usetheBUSYsignalasawriteinhibitsignal.ThusontheIDT70V659/58/ 57RAMtheBUSYpinisanoutputifthepartisusedasamaster(M/Spin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. NOTES: 1. A16 for IDT70V658. 2. A15 for IDT70V657. |
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