IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

18

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

NOTES:

4869 drw 16

INTERRUPT SET ADDRESS

R/

(3)

(4)

(3)

(2)

4869 drw 17

INTERRUPT CLEAR ADDRESS

(3)

(3)

(2)

Left Port

Right Port

Function

L

L

X

1FFFF

X

X

X

X

X

X

X

X

X

X

X

L

L

1FFFF

XX

X

X

L

L

X

1FFFE

X

X

L

L

1FFFE

X

X

X

X

X

4869 tbl 16