17

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

Waveform of BUSY Arbitration Cycle Controlled by Address Match

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

4869 drw 14

ADDRESSES MATCH

(2)

4869 drw 15

ADDRESS "N"

(2)

MATCHING ADDRESS "N"

70V659/58/57S10

Com'l Only

70V659/58/57S12

Com'l

& Ind

70V659/58/57S15

Com'l

& Ind

Symbol

Parameter

Min.Max.Min.

Max.

Min.Max.

Unit

INTERRUPT TIMING

Address Set-up Time

0

____

0

____

0

____

ns

Write Recovery Time

0

____

0

____

0

____

ns

Interrupt Set Time

____

10

____

12

____

15

ns

Interrupt Reset Time

____

10

____

12

____

15

ns

4869 tbl 15