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70V657S12DRGI8 Datasheet(PDF) 14 Page - Integrated Device Technology |
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70V657S12DRGI8 Datasheet(HTML) 14 Page - Integrated Device Technology |
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14 / 24 page  IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 14 Timing Waveform of Semaphore Read after Write Timing, Either Side(1) NOTES: 1. DOR = DOL = VIL, CEL = CER = VIH. Refer to Truth Table II for appropriate BE controls. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag. Timing Waveform of Semaphore Write Contention(1,3,4) NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate BE controls. 2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O35) equal to the semaphore value. SEM/BEn(1) 4869 drw 10 tAW tEW I/O VALID ADDRESS tSAA R/ W tWR tOH tACE VALID ADDRESS DATA VALID IN DATAOUT tDW tWP tDH tAS tSWRD tAOE Read Cycle Write Cycle A0-A2 OE VALID(2) tSOP tSOP SEM"A" 4869 drw 11 tSPS MATCH R/ W"A" MATCH A0"A"-A2"A" SIDE "A" (2) SEM"B" R/ W"B" A0"B"-A2"B" SIDE "B" (2) |
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