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IDT7005S Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT7005S Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 21 page  6.42 IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 11 Timing Waveform of Semaphore Read after Write Timing, Either Side(1) Timing Waveform of Semaphore Write Contention(1,3,4) NOTE: 1. CE = VIH for the duration of the above timing (both write and read cycle). NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start. 2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite from port “A”. 3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. SEM 2738 drw 11 tAW tEW tSOP DATA0 VALID ADDRESS tSAA R/ W tWR tOH VALID ADDRESS DATAIN VALID DATA OUT tDW tWP tDH tAS tSWRD tAOE tSOP Read Cycle Write Cycle A0-A2 OE VALID tACE SEM"A" 2738 drw 12 tSPS MATCH R/ W"A" MATCH A0"A"-A2"A" SIDE “A” (2) SEM"B" R/ W"B" A0"B"-A2"B" SIDE “B” (2) |
Similar Part No. - IDT7005S_18 |
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Similar Description - IDT7005S_18 |
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