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IDT7005S Datasheet(PDF) 16 Page - Integrated Device Technology |
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IDT7005S Datasheet(HTML) 16 Page - Integrated Device Technology |
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16 / 21 page  6.42 IDT7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 16 Truth Table IV — Address BUSY Arbitration NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7005 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functional Description TheIDT7005providestwoportswithseparatecontrol,addressand I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation inmemory.TheIDT7005hasanautomaticpowerdownfeaturecontrolled by CE. The CE controls on-chip power down circuitry that permits the respectiveporttogointoastandbymodewhennotselected(CEHIGH). Whenaportisenabled,accesstotheentirememoryarrayispermitted. Interrupts Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE (HEX), where a write is defined as CE = R/W= VIL per Truth Table III. Theleftportclearstheinterruptthroughaccessofaddresslocation1FFE when CE = OE = VIL. For this example, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 1FFF (HEX) and to clear the interrupt flag (INTR), the rightportmustreadthememorylocation1FFF.Themessage(8bits)at 1FFEor1FFFisuser-defined,sinceitisanaddressableSRAMlocation. Iftheinterruptfunctionisnotused,addresslocations1FFEand1FFFare notusedasmailboxes,butaspartoftherandomaccessmemory.Refer to Truth Table III for the interrupt operation. NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2. 3. CE=VIH, SEM=VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table. Inputs Outputs Function CEL CER AOL-A12L AOR-A12R BUSYL(1) BUSYR(1) X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 2738 tbl 18 Functions D0 - D7 Left D0 - D7 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free 2738 tbl 19 |
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