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IDT70V05S Datasheet(PDF) 12 Page - Integrated Device Technology

Part # IDT70V05S
Description  HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
Download  23 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70V05S Datasheet(HTML) 12 Page - Integrated Device Technology

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6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
12
T im ing Wa ve for m of Se m a phore Re a d a ft e r Writ e T im ing, Eit he r Side (1)
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
T im ing Wa ve for m of Se m a phore Writ e Cont e nt ion(1,3,4)
SEM"A"
2941 drw 11
tSPS
MATCH
R/W"A"
MATCH
A0"A"-A2"A"
SIDE
"A"
(2)
SEM"B"
R/W"B"
A0"B"-A2"B"
SIDE
"B"
(2)
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3.
This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
SEM
2941 drw 10
tAW
tEW
tSOP
DATA0
VALID ADDRESS
tSAA
R/W
tWR
tOH
ttACE
VALID ADDRESS
DATAIN VALID
DATA OUT
tDW
tWP
tDH
tAS
tSWRD
tAOE
tSOP
Read Cycle
Write Cycle
A0-A2
OE
VALID(2)


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