6.42

IDT70V05S/L

High-Speed 3.3V 8K x 8 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

11

NOTES:

1. R/W or CE must be HIGH during all address transitions.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE, or R/W.

7. Timing depends on which enable signal is de-asserted first, CE, or R/W.

2941 drw 09

ADDRESS

R/W

(3)

(2)

(6)

(9)

R/W

(2)

OE

ADDRESS

CE

(6)

(4)

(4)

(3)

2941 drw 08

(7)

(7)

(9)