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IDT70V05S Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70V05S Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 23 page  ©2018 Integrated Device Technology, Inc. M ARCH 2 0 1 8 DSC 2941/11 1 IDT70V05S/L HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT70V05S Active: 400mW (typ.) Standby: 3.3mW (typ.) – IDT70V05L Active: 380mW (typ.) Standby: 660 µW (typ.) ◆ ◆ ◆ ◆ ◆ IDT70V05 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Interrupt Flag ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ TTL-compatible, single 3.3V (±0.3V) power supply ◆ ◆ ◆ ◆ ◆ Available in 68-pin PGA and PLCC, and a 64-pin TQFP ◆ ◆ ◆ ◆ ◆ Industrial temperature range (-40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available, see ordering information Func t iona l Block Dia gra m NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/WL CEL OEL BUSYL A12L A0L 2942 drw 01 I/O0L- I/O7L CEL OEL R/WL SEML INTL M/S BUSYR I/O0R-I/O7R A12R A0R SEMR INTR CER OER (2) (1,2) (1,2) (2) R/WR CER OER 13 13 R/WR , LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 |
Similar Part No. - IDT70V05S_18 |
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Similar Description - IDT70V05S_18 |
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