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S1D13706 Datasheet(PDF) 57 Page - Epson Company |
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S1D13706 Datasheet(HTML) 57 Page - Epson Company |
57 / 152 page ![]() Epson Research and Development Page 57 Vancouver Design Center Hardware Functional Specification S1D13706 Issue Date: 2004/02/09 X31B-A-001-09 1. For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16. For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8. 2. The following formulas must be valid for all panel timings: HDPS + HDP < HT VDPS + VDP < VT Table 6-16: Panel Timing Parameter Definition and Register Summary Symbol Description Derived From Units HT Horizontal Total ((REG[12h] bits 6-0) + 1) x 8 Ts HDP1 Horizontal Display Period1 ((REG[14h] bits 6-0) + 1) x 8 HDPS Horizontal Display Period Start Position For STN panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 22) For TFT panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 5) HPS FPLINE Pulse Start Position (REG[23h] bits 1-0, REG[22h] bits 7-0) + 1 HPW FPLINE Pulse Width (REG[20h] bits 6-0) + 1 VT Vertical Total (REG[19h] bits 1-0, REG[18h] bits 7-0) + 1 Lines (HT) VDP Vertical Display Period (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 VDPS Vertical Display Period Start Position REG[1Fh] bits 1-0, REG[1Eh] bits 7-0 VPS FPFRAME Pulse Start Position REG[27h] bits 1-0, REG[26h] bits 7-0 VPW FPFRAME Pulse Width (REG[24h] bits 6-0) + 1 |
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