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S1D13706 Datasheet(PDF) 55 Page - Epson Company |
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S1D13706 Datasheet(HTML) 55 Page - Epson Company |
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55 / 152 page  Epson Research and Development Page 55 Vancouver Design Center Hardware Functional Specification S1D13706 Issue Date: 2004/02/09 X31B-A-001-09 6.3.2 Passive/TFT Power-Off Sequence Figure 6-12: Passive/TFT Power-Off Sequence Timing 1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected. Table 6-15: Passive/TFT Power-Off Sequence Timing Symbol Parameter Min Max Units t1 LCD bias deactivated to LCD signals inactive Note 1 Note 1 t2 Power Save Mode enabled to LCD signals low 020 ns LCD Signals*** GPO* t1 *It is recommended to use the general purpose output pin GPO to control the LCD bias power. **The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 1. ***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY. t2 Power Save (REG[A0h] bit 0) Mode Enable** |
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