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S1D13706 Datasheet(PDF) 50 Page - Epson Company |
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S1D13706 Datasheet(HTML) 50 Page - Epson Company |
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50 / 152 page  Page 50 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B-A-001-09 Issue Date: 2004/02/09 1. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer. Table 6-12: Motorola DragonBall Interface with DTACK Timing Symbol Parameter MC68EZ328 MC68VZ328 Unit 2.0V 3.3V 2.0V 3.3V Min Max Min Max Min Max Min Max fCLKO Bus Clock frequency 16 16 20 33 MHz TCLKO Bus Clock period 1/fCLKO 1/fCLKO 1/fCLKO 1/fCLKO ns t1 Clock pulse width high 28.1 28.1 22.5 13.5 ns t2 Clock pulse width low 28.1 28.1 22.5 13.5 ns t3 A[16:1] setup 1st CLKO when CSX = 0 and either UWE/LWE or OE = 0 0000 ns t4 A[16:1] hold from CSX rising edge 0000 ns t5a CSX asserted for MCLK = BCLK 8888 TCLKO t5b CSX asserted for MCLK = BCLK ÷ 2 11111111 TCLKO t5c CSX asserted for MCLK = BCLK ÷ 3 13131313 TCLKO t5d CSX asserted for MCLK = BCLK ÷ 4 17171717 TCLKO t6 CSX setup to CLKO rising edge 0000 ns t7 CSX rising edge to CLKO rising edge 0000 ns t8 UWE/LWE falling edge to CLKO rising edge 1010 ns t9 UWE/LWE rising edge to CSX rising edge 0000 ns t10 OE falling edge to CLKO rising edge 1111 ns t11 OE hold from CSX rising edge 0000 ns t12 D[15:0] setup to 3rd CLKO when CSX, UWE/LWE asserted (write cycle) (see note 1) 1010 ns t13 D[15:0] in hold from CSX rising edge (write cycle) 0000 ns t14 Falling edge of OE to D[15:0] driven (read cycle) 4 30 3 15 4 30 3 15 ns t15 CLKO rising edge to D[15:0] output Hi-Z (read cycle) 4 21 2 12 4 21 2 12 ns t16 CSX falling edge to DTACK driven high 3 20 3 13 3 20 3 13 ns t17 DTACK falling edge to D[15:0] valid (read cycle) 0202 ns t18 CSX high to DTACK high 5 34 3 16 5 34 3 16 ns t19 CLKO rising edge to DTACK Hi-Z 5 40 165 40 16 ns |
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