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S1D13706 Datasheet(PDF) 48 Page - Epson Company |
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S1D13706 Datasheet(HTML) 48 Page - Epson Company |
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48 / 152 page  Page 48 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B-A-001-09 Issue Date: 2004/02/09 1. t8 is the delay from when data is placed on the bus until the data is latched into the write buffer. Table 6-11: Motorola REDCAP2 Interface Timing Symbol Parameter 2.0V 3.3V Units Min Max Min Max fCKO Bus Clock frequency 17 17 MHz TCKO Bus Clock period 1/fCKO 1/fCKO ns t1 Bus Clock pulse width low 26 26 ns t2 Bus Clock pulse width high 26 26 ns t3 A[16:1], M/R#, R/W, CSn setup to CKO rising edge 11 ns t4 A[16:1], M/R#, R/W, CSn hold from CKO rising edge 00 ns t5a CSn asserted for MCLK = BCLK 88 TCKO t5b CSn asserted for MCLK = BCLK ÷ 2 10 10 TCKO t5c CSn asserted for MCLK = BCLK ÷ 3 13 13 TCKO t5d CSn asserted for MCLK = BCLK ÷ 4 15 15 TCKO t6 EB0, EB1 asserted to CKO rising edge (write cycle) 11 ns t7 EB0, EB1 de-asserted to CKO rising edge (write cycle) 14 ns t8 D[15:0] input setup to 3rd CKO rising edge after EB0 or EB1 asserted low (write cycle) (see note 1) 10 ns t9 D[15:0] input hold from 3rd CKO rising edge after EB0 or EB1 asserted low (write cycle) 23 8 ns t10 OE, EB0, EB1 setup to CKO rising edge (read cycle) 10 ns t11 OE, EB0, EB1 hold to CKO rising edge (read cycle) 10 ns t12 D[15:0] output delay from OE, EB0, EB1 falling edge (read cycle) 4293 10 ns t13a 1st CKO rising edge after EB0 or EB1 asserted low to D[15:0] valid for MCLK = BCLK (read cycle) 4.5CKO + 7 4.5CKO + 20 ns t13b 1st CKO rising edge after EB0 or EB1 asserted low to D[15:0] valid for MCLK = BCLK ÷ 2 (read cycle) 7CKO + 10 6.5CKO + 20 ns t13c 1st CKO rising edge after EB0 or EB1 asserted low to D[15:0] valid for MCLK = BCLK ÷ 3 (read cycle) 8.5CKO + 8 9.5CKO + 20 ns t13d 1st CKO rising edge after EB0 or EB1 asserted low to D[15:0] valid for MCLK = BCLK ÷ 4 (read cycle) 9CKO + 11 11.5CKO + 20 ns t14 CKO rising edge to D[15:0] output in Hi-Z (read cycle) 4311 11 ns |
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