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S1D13706 Datasheet(PDF) 38 Page - Epson Company |
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S1D13706 Datasheet(HTML) 38 Page - Epson Company |
38 / 152 page ![]() Page 38 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B-A-001-09 Issue Date: 2004/02/09 1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer. Table 6-6: Generic #2 Interface Timing Symbol Parameter 2.0V 3.3V Unit MinMax MinMax fBUSCLK Bus Clock frequency 20 50 MHz TBUSCLK Bus Clock period 1/fBUSCLK 1/fBUSCLK ns t1 Clock pulse width high 22.5 9 ns t2 Clock pulse width low 22.5 9 ns t3 SA[16:0], M/R#, SBHE# setup to first BUSCLK rising edge where CS# = 0 and either MEMR# = 0 or MEMW# = 0 11 ns t4 SA[16:0], M/R#, SBHE# hold from either MEMR# or MEMW# rising edge 00 ns t5 CS# setup to BUSCLK rising edge 0 1 ns t6 CS# hold from either MEMR# or MEMW# rising edge 0 0 ns t7a MEMR#/MEMW# asserted for MCLK = BCLK 8.5 8 TBUSCLK t7b MEMR#/MEMW# asserted for MCLK = BCLK ÷ 211.5 11 TBUSCLK t7c MEMR#/MEMW# asserted for MCLK = BCLK ÷ 313.5 13 TBUSCLK t7d MEMR#/MEMW# asserted for MCLK = BCLK ÷ 417.5 17 TBUSCLK t8 MEMR# or MEMW# setup to BUSCLK rising edge 2 1 ns t9 Falling edge of either MEMR# or MEMW# to IOCHRDY driven low 5 3 15 ns t10 Rising edge of either MEMR# or MEMW# to IOCHRDY high impedance 5 3 13 ns t11 SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and MEMW# = 0 (write cycle) (see note 1) 10 ns t12 SD[15:0] hold from IOCHRDY rising edge (write cycle) 1 0 ns t13 MEMR# falling edge to SD[15:0] driven (read cycle) 4 26 3 13 ns t14 IOCHRDY rising edge to SD[15:0] valid (read cycle) 0 2 ns t15 Rising edge of MEMR# to SD[15:0] high impedance (read cycle) 5 33 3 12 ns |
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