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S1D13706 Datasheet(PDF) 36 Page - Epson Company |
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S1D13706 Datasheet(HTML) 36 Page - Epson Company |
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36 / 152 page  Page 36 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B-A-001-09 Issue Date: 2004/02/09 1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer. Table 6-5: Generic #1 Interface Timing Symbol Parameter 2.0V 3.3V Unit Min Max Min Max fCLK Bus Clock frequency 20 50 MHz TCLK Bus Clock period 1/fCLK 1/fCLK ns t1 Clock pulse width high 22.5 9 ns t2 Clock pulse width low 22.5 9 ns t3 A[16:1], M/R# setup to first CLK rising edge where CS# = 0 and either RD0#, RD1# = 0 or WE0#, WE1# = 0 11 ns t4 A[16:1], M/R# hold from either RD0#, RD1# or WE0#, WE1# rising edge 00 ns t5 CS# setup to CLK rising edge 0 1 ns t6 CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge 0 0 ns t7a RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK 8.5 8.5 TCLK t7b RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷ 2 11.5 11.5 TCLK t7c RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷ 3 13.5 13.5 TCLK t7d RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷ 4 17.5 17.5 TCLK t8 RD0#, RD1#, WE0#, WE1# setup to CLK rising edge 2 1 ns t9 Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT# driven low 5 31 3 15 ns t10 Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# high impedance 5 34 3 13 ns t11 D[15:0] setup to third CLK rising edge where CS# = 0 and WE0#, WE1# = 0 (write cycle) (see note 1) 10 ns t12 D[15:0] hold from WAIT# rising edge (write cycle) 1 0 ns t13 RD0#, RD1# falling edge to D[15:0] driven (read cycle) 4 27 3 14 ns t14 WAIT# rising edge to D[15:0] valid (read cycle) 0 2 ns t15 RD0#, RD1# rising edge to D[15:0] high impedance (read cycle) 3 29 3 11 ns |
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