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S1D13706 Datasheet(PDF) 32 Page - Epson Company |
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S1D13706 Datasheet(HTML) 32 Page - Epson Company |
32 / 152 page ![]() Page 32 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B-A-001-09 Issue Date: 2004/02/09 6 A.C. Characteristics Conditions: HIO VDD = 2.0V ± 10% and HIO VDD = 3.3V ± 10% NIO VDD = 3.3V ± 10% TA = -40° C to 85° C Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%) CL = 50pF (Bus/MPU Interface) CL = 0pF (LCD Panel Interface) 6.1 Clock Timing 6.1.1 Input Clocks Figure 6-1: Clock Input Requirements Note Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page 34 for internal clock requirements. Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1 Symbol Parameter 2.0V 3.3V Units MinMax MinMax f OSC Input Clock Frequency (CLKI) 40 100 MHz T OSC Input Clock period (CLKI) 1/f OSC 1/f OSC ns t PWH Input Clock Pulse Width High (CLKI) 4.5 4.5 ns t PWL Input Clock Pulse Width Low (CLKI) 4.5 4.5 ns t f Input Clock Fall Time (10% - 90%) 5 5 ns t r Input Clock Rise Time (10% - 90%) 5 5 ns t PWL t PWH t f Clock Input Waveform tr TOSC V IH VIL 10% 90% |
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