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S1D13706 Datasheet(PDF) 27 Page - Epson Company |
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S1D13706 Datasheet(HTML) 27 Page - Epson Company |
27 / 152 page Epson Research and Development Page 27 Vancouver Design Center Hardware Functional Specification S1D13706 Issue Date: 2004/02/09 X31B-A-001-09 4.3.3 Clock Input 4.3.4 Miscellaneous 4.3.5 Power And Ground Table 4-4: Clock Input Pin Descriptions Pin Name Type Pin # Cell IO Voltage RESET# State Description CLKI I 15 LI NIOVDD — Typically used as input clock source for bus clock and memory clock CLKI2 I 77 LI NIOVDD — Typically used as input clock source for pixel clock Table 4-5: Miscellaneous Pin Descriptions Pin Name Type Pin # Cell IO Voltage RESET# State Description CNF[7:0] I 78-85 LI NIOVDD — These inputs are used to configure the S1D13706 - see Table 4-7: “Summary of Power-On/Reset Options,” on page 28. Note: These pins are used for configuration of the S1D13706 and must be connected directly to IO VDD or VSS. GPO O 47 LO3 NIOVDD 0 General Purpose Output (possibly used for controlling the LCD power). It may also be used for the MOD control signal of the Sharp HR-TFT panel. TESTEN I 86 T1 NIOVDD 0 Test Enable input used for production test only (has type 1 pull- down resistor with a typical value of 50 Ω at 3.3V). Table 4-6: Power And Ground Pin Descriptions Pin Name Type Pin # Cell IO Voltage RESET# State Description HIOVDD P 16, 26 P — — IO VDD pins associated with the host interface pins as described in Section 4.3.1, “Host Interface” on page 21. NIOVDD P 37, 49, 63, 76 P— — IO VDD pins associated with the non-host interface pins as described in Section 4.3.2, “LCD Interface” on page 25, Section 4.3.3, “Clock Input” on page 27, and Section 4.3.4, “Miscellaneous” on page 27. COREVDD P 1, 51 P — — 2 Core VDD. pins. VSS P 14, 25, 36, 50, 62, 75, 100 P— — 7 VSS pins. |
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