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S1D13706 Datasheet(PDF) 24 Page - Epson Company

Part # S1D13706
Description  S1D13706 Embedded Memory LCD Controller
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Manufacturer  EPSON [Epson Company]
Direct Link  http://www.epsondevice.com
Logo EPSON - Epson Company

S1D13706 Datasheet(HTML) 24 Page - Epson Company

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Page 24
Epson Research and Development
Vancouver Design Center
S1D13706
Hardware Functional Specification
X31B-A-001-09
Issue Date: 2004/02/09
WAIT#
O
17
LB2A
HIOVDD
Hi-Z
During a data transfer, this output pin is driven active to force the
system to insert wait states. It is driven inactive to indicate the
completion of a data transfer. WAIT# is released to the high
impedance state after the data transfer is complete. Its active
polarity is configurable. See Table 4-7: “Summary of Power-
On/Reset Options,” on page 28.
• For Generic #1, this pin outputs the wait signal (WAIT#).
• For Generic #2, this pin outputs the wait signal (WAIT#).
• For SH-3 mode, this pin outputs the wait request signal
(WAIT#).
• For SH-4 mode, this pin outputs the device ready signal
(RDY#).
• For MC68K #1, this pin outputs the data transfer acknowledge
signal (DTACK#).
• For MC68K #2, this pin outputs the data transfer and size
acknowledge bit 1 (DSACK1#).
• For REDCAP2, this pin is unused (Hi-Z).
• For DragonBall, this pin outputs the data transfer
acknowledge signal (DTACK).
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
RESET#
I
13
LIS
HIOVDD
0
Active low input to set all internal registers to the default state and
to force all signals to their inactive states.
Table 4-2: Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
Voltage
RESET#
State
Description


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