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S1D13706 Datasheet(PDF) 12 Page - Epson Company |
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S1D13706 Datasheet(HTML) 12 Page - Epson Company |
12 / 152 page ![]() Page 12 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B-A-001-09 Issue Date: 2004/02/09 2 Features 2.1 Integrated Frame Buffer • Embedded 80K byte SRAM display buffer. 2.2 CPU Interface • Direct support of the following interfaces: Generic MPU bus interface using WAIT# signal. Hitachi SH-3. Hitachi SH-4. Motorola M68K. Motorola MC68EZ328/MC68VZ328 DragonBall. Motorola “REDCAP2” - no WAIT# signal. • 8-bit processor support with “glue logic”. • “Fixed” low-latency CPU access times. • Registers are memory-mapped - M/R# input selects between memory and register address space. • The complete 80K byte display buffer is directly and contiguously available through the 17-bit address bus. • Single level CPU write buffer. 2.3 Display Support • Single-panel, single-drive passive displays. • 4/8-bit monochrome LCD interface. • 4/8/16-bit color LCD interface. • Active Matrix TFT interface. • 9/12/18-bit interface. • ‘Direct’ support for 18-bit Epson D-TFD interface. • ‘Direct’ support for 18-bit Sharp HR-TFT interface. |
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