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S1D13706 Datasheet(PDF) 97 Page - Epson Company |
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S1D13706 Datasheet(HTML) 97 Page - Epson Company |
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97 / 152 page  Epson Research and Development Page 97 Vancouver Design Center Hardware Functional Specification S1D13706 Issue Date: 2004/02/09 X31B-A-001-09 bits 7-0 Display Buffer Size Bits [7:0] This is a read-only register that indicates the size of the SRAM display buffer measured in 4K byte increments. The S1D13706 display buffer is 80K bytes and therefore this register returns a value of 20 (14h). Value of this register = display buffer size ÷ 4K bytes = 80K bytes ÷ 4K bytes = 20 (14h) bits 7-0 CNF[7:0] Status These read-only status bits return the status of the configuration pins CNF[7:0]. CNF[7:0] are latched at the rising edge of RESET#. 8.3.2 Clock Configuration Registers bits 5-4 MCLK Divide Select Bits [1:0] These bits determine the divide used to generate the Memory Clock (MCLK) from the Bus Clock (BCLK). bit 0 Reserved. This bit must remain at 0. Display Buffer Size Register REG[01h] Read Only Display Buffer Size Bits 7-0 765 43210 Configuration Readback Register REG[02h] Read Only CNF7 Status CNF6 Status CNF5 Status CNF4 Status CNF3 Status CNF2 Status CNF1 Status CNF0 Status 76 543 210 Memory Clock Configuration Register REG[04h] Read/Write n/a MCLK Divide Select Bits 1-0 n/a Reserved 7 65 4 3 2 10 Table 8-2: MCLK Divide Selection MCLK Divide Select Bits BCLK to MCLK Frequency Ratio 00 1:1 01 2:1 10 3:1 11 4:1 |
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