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S1D13706 Datasheet(PDF) 93 Page - Epson Company |
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S1D13706 Datasheet(HTML) 93 Page - Epson Company |
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93 / 152 page  Epson Research and Development Page 93 Vancouver Design Center Hardware Functional Specification S1D13706 Issue Date: 2004/02/09 X31B-A-001-09 7.2 Clock Selection The following diagram provides a logical representation of the S1D13706 internal clocks. Figure 7-1: Clock Selection Note 1 CNF[7:6] must be set at RESET#. CLKI CLKI2 ÷2 ÷3 ÷4 00 01 10 11 BCLK ÷2 ÷3 ÷4 00 01 10 11 MCLK 00 01 10 11 ÷2 ÷3 ÷4 000 001 010 011 ÷8 1xx 0 1 PCLK PWMCLK REG[05h] bits 1,0 REG[B1h] bit 0 REG[05h] bits 6-4 REG[04h] bits 5,4 CNF[7:6]1 |
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