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S1D13706 Datasheet(PDF) 92 Page - Epson Company |
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S1D13706 Datasheet(HTML) 92 Page - Epson Company |
92 / 152 page ![]() Page 92 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B-A-001-09 Issue Date: 2004/02/09 There is a relationship between the frequency of MCLK and PCLK that must be maintained. 7.1.4 PWMCLK PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel. The source clock options for PWMCLK may be selected as in the following table. For further information on controlling PWMCLK, see Section 8.3.9, “Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers” on page 126. Note The S1D13706 provides Pulse Width Modulation output on the pin PWMOUT. PWMOUT can be used to control LCD panels which support PWM control of the back- light inverter. Table 7-4: Relationship between MCLK and PCLK SwivelView Orientation Color Depth (bpp) MCLK to PCLK Relationship SwivelView 0° and 180° 16 fMCLK ≥ fPCLK 8fMCLK ≥ fPCLK ÷ 2 4fMCLK ≥ fPCLK ÷ 4 2fMCLK ≥ fPCLK ÷ 8 1fMCLK ≥ fPCLK ÷16 SwivelView 90° and 270° 16/8/4/2/1 fMCLK ≥ 1.25fPCLK Table 7-5: PWMCLK Clock Selection Source Clock Options PWMCLK Selection CLKI REG[B1h] bit 0 = 0 CLKI2 REG[B1h] bit 0 = 1 |
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