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S1D13706 Datasheet(PDF) 91 Page - Epson Company |
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S1D13706 Datasheet(HTML) 91 Page - Epson Company |
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91 / 152 page  Epson Research and Development Page 91 Vancouver Design Center Hardware Functional Specification S1D13706 Issue Date: 2004/02/09 X31B-A-001-09 7.1.3 PCLK PCLK is the internal clock used to control the LCD panel. PCLK should be chosen to match the optimum frame rate of the LCD panel. See Section 9, “Frame Rate Calculation” on page 130 for details on the relationship between PCLK and frame rate. Some flexibility is possible in the selection of PCLK. Firstly, LCD panels typically have a range of permissible frame rates. Secondly, it may be possible to choose a higher PCLK frequency and tailor the horizontal and vertical non-display periods to lower the frame-rate to its optimal value. The source clock options for PCLK may be selected as in the following table. Table 7-3: PCLK Clock Selection Source Clock Options PCLK Selection MCLK REG[05h] = 00h MCLK ÷2 REG[05h] = 10h MCLK ÷3 REG[05h] = 20h MCLK ÷4 REG[05h] = 30h MCLK ÷8 REG[05h] = 40h BCLK REG[05h] = 01h BCLK ÷2 REG[05h] = 11h BCLK ÷3 REG[05h] = 21h BCLK ÷4 REG[05h] = 31h BCLK ÷8 REG[05h] = 41h CLKI REG[05h] = 02h CLKI ÷2 REG[05h] = 12h CLKI ÷3 REG[05h] = 22h CLKI ÷4 REG[05h] = 32h CLKI ÷8 REG[05h] = 42h CLKI2 REG[05h] = 03h CLKI2 ÷2 REG[05h] = 13h CLKI2 ÷3 REG[05h] = 23h CLKI2 ÷4 REG[05h] = 33h CLKI2 ÷8 REG[05h] = 43h |
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