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S1D13706 Datasheet(PDF) 75 Page - Epson Company |
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S1D13706 Datasheet(HTML) 75 Page - Epson Company |
75 / 152 page ![]() Epson Research and Development Page 75 Vancouver Design Center Hardware Functional Specification S1D13706 Issue Date: 2004/02/09 X31B-A-001-09 1. Ts = pixel clock period 2. t6min = HDPS - HPS if negative add HT 3. t8min = HPS - (HDP + HDPS) if negative add HT Table 6-23: TFT A.C. Timing Symbol Parameter Min Typ Max Units t1 FPFRAME cycle time VT Lines t2 FPFRAME pulse width low VPW Lines t3 FPFRAME falling edge to FPLINE falling edge phase difference HPS Ts (note 1) t4 FPLINE cycle time HT Ts t5 FPLINE pulse width low HPW Ts t6 FPLINE Falling edge to DRDY active note 2 250 Ts t7 DRDY pulse width HDP Ts t8 DRDY falling edge to FPLINE falling edge note 3 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width high 0.5 Ts t11 FPSHIFT pulse width low 0.5 Ts t12 FPLINE setup to FPSHIFT falling edge 0.5 Ts t13 DRDY to FPSHIFT falling edge setup time 0.5 Ts t14 DRDY hold from FPSHIFT falling edge 0.5 Ts t15 Data setup to FPSHIFT falling edge 0.5 Ts t16 Data hold from FPSHIFT falling edge 0.5 Ts |
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