S1D13706 datasheet(73/152 Pages) EPSON

Part #	S1D13706

Description	S1D13706 Embedded Memory LCD Controller

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Manufacturer	EPSON [Epson Company]

Direct Link	http://www.epsondevice.com

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Epson Research and Development

Page 73

Vancouver Design Center

Hardware Functional Specification

S1D13706

Issue Date: 2004/02/09

X31B-A-001-09

6.4.9 9/12/18-Bit TFT Panel Timing

Figure 6-28: 18-Bit TFT Panel Timing

VDP

= Vertical Display Period

= VDP Lines

VNDP

= Vertical Non-Display Period

= VNDP1 + VNDP2

= VT - VDP Lines

VNDP1

= Vertical Non-Display Period 1

= VNDP - VNDP2 Lines

VNDP2

= Vertical Non-Display Period 2

= VDPS - VPS Lines

if negative add VT

HDP

= Horizontal Display Period

= HDP Ts

HNDP

= Horizontal Non-Display Period

= HNDP1 + HNDP2

= HT - HDP Ts

HNDP1

= Horizontal Non-Display Period 1

= HDPS - HPS Ts

if negative add HT

HNDP2

= Horizontal Non-Display Period 2

= HPS - (HDP + HDPS) Ts

if negative add HT

FPFRAME

FPLINE

LINE1

LINE480

1-1

1-2

1-320

FPLINE

FPSHIFT

DRDY

FPDAT[17:0]

VDP

DRDY

Note: DRDY is used to indicate the first pixel

Example Timing for 18-bit 320x240 panel

VNDP2

HDP

HNDP1

HNDP2

LINE240

VNDP1

FPDAT[17:0]

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