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S1D13706 Datasheet(PDF) 67 Page - Epson Company |
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S1D13706 Datasheet(HTML) 67 Page - Epson Company |
67 / 152 page Epson Research and Development Page 67 Vancouver Design Center Hardware Functional Specification S1D13706 Issue Date: 2004/02/09 X31B-A-001-09 Figure 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1) 1. Ts = pixel clock period 2. t1min = HPS + t4min 3. t2min = t3min - (HPS + t4min) 4. t3min = HT 5. t4min = HPW 6. t6amin = HPS - (HDP + HDPS), if negative add t3min 7. t6bmin = HPS - (HDP + HDPS) + 2, if negative add t3min 8. t14min = HDPS - (HPS + t4min), if negative add t3min Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1) Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 Ts (note 1) t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t6a FPSHIFT falling edge to FPLINE rising edge note 6 Ts t6b FPSHIFT2 falling edge to FPLINE rising edge note 7 Ts t7a FPSHIFT falling edge to FPLINE falling edge t6a + t4 Ts t7b FPSHIFT2 falling edge to FPLINE falling edge t6b + t4 Ts t8 FPLINE falling edge to FPSHIFT rising, FPSHIFT2 falling edge t14 + 2 Ts t9 FPSHIFT2, FPSHIFT period 4 6 Ts t10 FPSHIFT2, FPSHIFT pulse width low 2 Ts t11 FPSHIFT2, FPSHIFT pulse width high 2 Ts t12 FPDAT[7:0] setup to FPSHIFT2, FPSHIFT falling edge 1 Ts t13 FPDAT[7:0] hold from FPSHIFT2, FPSHIFT falling edge 1 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts FPFRAME FPLINE Sync Timing FPLINE FPSHIFT FPDAT[7:0] Data Timing t14 t1 t2 t3 t4 t8 t9 t10 t11 t12 t13 2 1 t7a t6b FPSHIFT2 t6a t7b t12 t13 |
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