EDS2532AABJ-6B datasheet(7/48 Pages) ELPIDA

Part #	EDS2532AABJ-6B

Description	256M bits SDRAM (8M words 짰32 bits)

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Manufacturer	ELPIDA [Elpida Memory]

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EDS2532AABJ-6B

Data Sheet E0509E30 (Ver. 3.0)

7

AC Characteristics (TA = 0 to +70

°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)

-6B

Parameter

Symbol

min.

max.

Unit

Notes

System clock cycle time

(CL = 2)

tCK

—

ns

1

(CL = 3)

tCK

6

—

ns

1

CLK high pulse width

tCH

2.5

—

ns

1

CLK low pulse width

tCL

2.5

—

ns

1

Access time from CLK

tAC

—

5.4

ns

1, 2

Data-out hold time

tOH

2.0

—

ns

1, 2

CLK to Data-out low impedance

tLZ

0

—

ns

1, 2, 3

CLK to Data-out high impedance

tHZ

—

5.4

ns

1, 4

Input setup time

tSI

1.5

—

ns

1

Input hold time

tHI

0.8

—

ns

1

Ref/Active to Ref/Active command period

tRC

60

—

ns

1

Active to Precharge command period

tRAS

42

120000

ns

1

Active command to column command (same bank)

tRCD

18

—

ns

1

Precharge to active command period

tRP

18

—

ns

1

Write recovery or data-in to precharge lead time

tDPL

12

—

ns

1

Last data into active latency

tDAL

2CLK + 18ns —

Active (a) to Active (b) command period

tRRD

12

—

ns

1

Transition time (rise and fall)

tT

0.5

5.0

ns

Refresh period (4096 refresh cycles)

tREF

—

64

ms

Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.

2. Access time is measured at 1.4V. Load condition is CL = 30pF.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.

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