AD9524BCPZ datasheet(23/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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Data Sheet

AD9524

Rev. F | Page 23 of 56

CLOCK DISTRIBUTION

The clock distribution block provides an integrated solution for

generating multiple clock outputs based on frequency dividing

the PLL2 VCO divider output. The distribution output consists

of six channels (OUT0 to OUT5). Each of the output channels

has a dedicated divider and output driver, as shown in Figure 25.

The AD9524 also has the capability to route the VCXO output

to two of the outputs (OUT0 and OUT1).

Clock Dividers

The output clock distribution dividers are referred to as D0 to D5,

corresponding to output channels OUT0 through OUT5,

respectively. Each divider is programmable with 10 bits of division

depth that is equal to 1 to 1024. Dividers have duty cycle correction

to always give 50% duty cycle, even for odd divides.

Output Power-Down

Each of the output channels offers independent control of the

power-down functionality via the Channel 0 to Channel 5 control

registers (see Table 52). Each output channel has a dedicated

power-down bit for powering down the output driver. However,

if all six outputs are powered down, the entire distribution output

enters a deep sleep mode. Although each channel has a channel

power-down control signal, it may sometimes be desirable to

power down an output driver while maintaining the divider’s

synchronization with the other channel dividers. This is accom-

plished by placing the output in tristate mode (this works in

CMOS mode, as well).

Multimode Output Drivers

The user has independent control of the operating mode of each of

the fourteen output channels via the Channel 0 to Channel 5

control registers (see Table 52). The operating mode control

includes the following:

•

Logic family and pin functionality

•

Output drive strength

•

Output polarity

The four least significant bits (LSBs) of each of the six Channel 0 to

Channel 5 control registers comprise the driver mode bits. The

mode value selects the desired logic family and pin functionality

of an output channel, as listed in Table 52. This driver design

allows a common 100 Ω external resistor for all the different

driver modes of operation that are illustrated in Figure 26.

If the output channel is ac-coupled to the circuit to be clocked,

changing the mode varies the voltage swing to determine sensi-

tivity to the drive level. For example, in LVDS mode, a current of

3.5 mA causes a 350 mV peak voltage. Likewise, in LVPECL

compatible mode, a current of 8 mA causes an 800 mV peak

voltage at the 100 Ω load resistor. Using any termination other

than those specified in the Input/Output Termination

Recommendations section may results in damage or decrease

end of life performance.

In addition to the four mode bits, each of the six Channel 0 to

Channel 5 control registers includes the following control bits:

•

Invert divider output. Enables the user to choose between

normal polarity and inverted polarity. Normal polarity is the

default state. Inverted polarity reverses the representation of

Logic 0 and Logic 1, regardless of the logic family.

•

Ignore sync. Makes the divider ignore the SYNC signal

from any source.

•

Power-down channel. Powers down the entire channel.

•

Lower power mode.

•

Driver mode.

•

Channel divider.

•

Divider phase.

3.5mA/8mA

LVDS/LVPECL

ENABLED

HSTL

ENABLED

HSTL

ENABLED

50Ω

P

N

P

100Ω LOAD

CM

VDD3_OUT[x:y]

1.25V LVDS

VDD – 1.3V LVPECL

CM

COMMON-MODE

CIRCUIT

+

–

Figure 26. Multimode Driver

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