AD9524BCPZ datasheet(20/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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AD9524

Data Sheet

Rev. F | Page 20 of 56

COMPONENT BLOCKS—INPUT PLL (PLL1)

PLL1 General Description

Fundamentally, the input PLL (referred to as PLL1) consists of

a phase-frequency detector (PFD), charge pump, passive loop

filter, and an external VCXO operating in a closed loop.

PLL1 has the flexibility to operate with a loop bandwidth of

approximately 10 Hz to 100 Hz. This relatively narrow loop

bandwidth gives the AD9524 the ability to suppress jitter that

appears on the input references (REFA and REFB). The output

of PLL1 then becomes a low jitter phase-locked version of the

reference input system clock.

PLL1 Reference Clock Inputs

The AD9524 features two separate differential reference clock

inputs, REFA and REFB. These inputs can be configured to

operate in full differential mode or single-ended CMOS mode.

In differential mode, these pins are internally self biased. If

REFA or REFB is driven single-ended, the unused side (REFA,

REFB) should be decoupled via a suitable capacitor to a quiet

ground. Figure 21 shows the equivalent circuit of REFA or REFB.

It is possible to dc couple to these inputs, but the dc operation

point should be set as specified in the Specifications tables.

To operate either the REFA or the REFB inputs in 3.3 V CMOS

mode, the user must set Bit 5 or Bit 6, respectively, in Register

0x01A (see Table 41). The single-ended inputs can be driven by

either a dc-coupled CMOS level signal or an ac-coupled sine

wave or square wave.

The differential reference input receiver is powered down when

the differential reference input is not selected, or when the PLL

is powered down. The single-ended buffers power-down when

the PLL is powered down, when their respective individual power-

down registers are set, or when the differential receiver is selected.

The REFB R divider uses the same value as the REFA R divider

unless Bit 7, the enable REFB R divider independent division

control bit in Register 0x01C, is programmed as shown in Table 43.

PLL1 Loop Filter

The PLL1 loop filter requires the connection of an external

capacitor from LF1_EXT_CAP (Pin 5) to ground. The value of the

external capacitor depends on the use of an external VCXO, as

well as such configuration parameters as input clock rate and

desired bandwidth. Normally, a 0.3 µF capacitor allows the loop

bandwidth to range from 10 Hz to 100 Hz and ensures loop

stability over the intended operating parameters of the device

(see Table 44 for RZERO values).

RZERO

CPOLE1

RPOLE2

CPOLE2

CHARGE

PUMP

LF1_EXT_CAP

LDO_PLL1

BUFFER

1kΩ

0.3µF

OSC_CTRL

TO VCXO

VTUNE

AD9524

Figure 23. PLL1 Loop Filter

Table 20. PLL1 Loop Filter Programmable Values

RZERO

(kΩ)

CPOLE1

(nF)

RPOLE2

(kΩ)

CPOLE2

(nF)

LF1_EXT_CAP1

(µF)

883

1.5 fixed

165 fixed

0.337 fixed

0.3

677

341

135

10

External

1 External loop filter capacitor.

An external R-C low-pass filter should be used at the OSC_CTRL

output. The values shown in Figure 23 add an additional low-pass

pole at ~530 Hz. This R-C network filters the noise associated with

the OSC_CTRL buffer to achieve the best noise performance at the

1 kHz offset region.

RZERO

CPOLE1

RPOLE2

LF1_EXT_CAP

SWITCH-

OVER

CONTROL

REFA

REFB

REFA

REFB

REF_SEL

REF_TEST

DIVIDE BY

1, 2, ...1024

CHARGE

PUMP

7 BITS,

0.5µA LSB

VDD3_PLL1

LDO_PLL1

1.8V LDO

3.3V CMOS

OR 1.8V

DIFFERENTIAL

OSC_CTRL

OSC_IN

DIVIDE BY

1, 2, ...1024

DIVIDE BY

1, 2, ...1024

DIVIDE BY

1, 2, ...63

P

F

D

VCXO

CPOLE2

AD9524

Figure 24. Input PLL (PLL1) Block Diagram

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