AD9524BCPZ datasheet(14/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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Manufacturer	AD [Analog Devices]

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14 / 56 page

AD9524

Data Sheet

Rev. F | Page 14 of 56

No.

Mnemonic

Type1

Description

16

SCLK/SCL

I

Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial programming.

This pin has an internal 40 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode.

17

SDIO/SDA

I/O

Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I²C Mode (SDA).

18

SDO

O

Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode).

There is no internal pull-up/pull-down resistor on this pin.

19

OUT5

O

Complementary Clock Output 5. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

20

OUT5

O

Clock Output 5. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

21

VDD3_OUT[4:5]

P

3.3 V Supply for Output 4 and Output 5 Clock Drivers.

22

OUT4

O

Complementary Clock Output 4. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

23

OUT4

O

Clock Output 4. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

24

VDD1.8_OUT[4:5]

P

1.8 V Supply for Output 4 and Output 5 Clock Dividers.

25

REF_TEST

I

Test Input to PLL1 Phase Detector.

26

RESET

I

Digital Input, Active Low. Resets internal logic to default states. This pin has an internal

40 kΩ pull-up resistor.

27

PD

Chip Power-Down, Active Low. This pin has an internal 40 kΩ pull-up resistor.

28

EEPROM_SEL

I

EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to

be loaded at reset and/or power-up. Setting this pin low causes the

AD9524 to load the hard-

coded default register values at power-up/reset. This pin has an internal 40 kΩ pull-down resistor.

29

OUT3

O

Complementary Clock Output 3. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

30

OUT3

O

Square Wave Clocking Output 3. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

31

VDD3_OUT[2:3]

P

3.3 V Supply Output 2 and Supply Output 3 Clock Drivers.

32

OUT2

O

Complementary Clock Output 2. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

33

OUT2

O

Clock Output 2. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

34

VDD1.8_OUT[2:3]

P

1.8 V Supply for Output 2 and Output 3 Clock Dividers.

35

STATUS1/SP1

I/O

Lock Detect and Other Status Signals (STATUS1)/I2C Address (SP1).

36

STATUS0/SP0

I/O

Lock Detect and Other Status Signals (STATUS0)/I2C Address (SP0).

37

OUT1

O

Complementary Clock Output 1. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

38

OUT1

O

Clock Output 1. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

39

VDD3_OUT[0:1]

P

3.3 V Supply Output 0 and Supply Output 1 Clock Drivers.

40

OUT0

O

Complementary Clock Output 0. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

41

OUT0

O

Clock Output 0. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

42

VDD1.8_OUT[0:1]

P

1.8 V Supply for Output 0 and Output 1 Clock Dividers.

43

ZD_IN

I

External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input for the PLL

reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

44

ZD_IN

I

Complementary External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input

for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

45

REF_SEL

I

Reference Input Select. This pin has an internal 40 kΩ pull-down resistor.

46

PLL1_OUT

O

Single-Ended CMOS Output from PLL1. This pin has settings for weak and strong in

Register 0x1BA, Bit 4 (see

Table 53).

47

LDO_PLL1

P/O

1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 µF decoupling capacitor

from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be

placed in close proximity to the device.

48

VDD3_PLL1

P

3.3 V Supply PLL1. Use the same supply as VCXO.

EP

EP, GND

GND

Exposed Paddle. The exposed paddle is the ground connection on the chip. It must be soldered

to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and

mechanical strength benefits.

1 P = power, I = input, O = output, I/O = input/output, P/O = power/output, GND = ground.

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