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AD9524BCPZ Datasheet(PDF) 13 Page - Analog Devices |
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AD9524BCPZ Datasheet(HTML) 13 Page - Analog Devices |
13 / 56 page ![]() Data Sheet AD9524 Rev. F | Page 13 of 56 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 TOP VIEW (Not to Scale) AD9524 25 26 27 28 29 30 31 32 33 34 35 36 8 9 10 11 12 REFA REFA REFB REFB LF1_EXT_CAP OSC_CTRL OSC_IN OSC_IN LF2_EXT_CAP LDO_PLL2 VDD3_PLL2 LDO_VCO VDD1.8_OUT[2:3] OUT2 OUT2 VDD3_OUT[2:3] OUT3 OUT3 EEPROM_SEL PD RESET REF_TEST STATUS0/SP0 STATUS1/SP1 NOTES 1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. ON EXISTING PCB DESIGNS, IT ISACCEPTABLE TO LEAVE PIN 42 CONNECTED TO 1.8V SUPPLY. 2. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 2. Pin Configuration Table 19. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 REFA I Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 2 REFA I Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input. 3 REFB I Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 4 REFB I Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 5 LF1_EXT_CAP O PLL1 External Loop Filter Capacitor. Connect a loop filter capacitor to this pin and to ground. 6 OSC_CTRL O Oscillator Control Voltage. Connect this pinto the voltage control pin of the external oscillator. 7 OSC_IN I PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 8 OSC_IN I Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 9 LF2_EXT_CAP O PLL2 External Loop Filter Capacitor Connection. Connect a capacitor to this pin and LDO_VCO. 10 LDO_PLL2 P/O LDO Decoupling Pin for PLL2 1.8 V Internal Regulator. Connect a 0.47 μF decoupling capacitor from this pin to ground. Note that for best performance, the LDO bypass capacitor must be placed in close proximity to the device. 11 VDD3_PLL2 P 3.3 V Supply for PLL2. 12 LDO_VCO P/O 2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 μF decoupling capacitor from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close proximity to the device. 13 SYNC I Manual Synchronization. This pin initiates a manual synchronization and has an internal 40 kΩ pull-up resistor. 14 VDD3_REF P 3.3 V Supply for Output Clock Drivers Reference. 15 CS I Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor. |
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