AD9524BCPZ datasheet(9/56 Pages) AD

Part #	AD9524BCPZ

Description	Jitter Cleaner and Clock Generator

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Data Sheet

AD9524

Rev. F | Page 9 of 56

TIMING ALIGNMENT CHARACTERISTICS

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT TIMING SKEW

Delay off on all outputs; maximum deviation

between rising edges of outputs; all outputs are on,

unless otherwise noted.

Between LVPECL, HSTL, and LVDS Outputs

38

234

ps

Between CMOS Outputs

100

300

ps

Single-ended true phase high-Z mode

Adjustable Delay

0

63

Steps

Resolution step; for example, 8 × 0.5/1 GHz

Resolution Step

500

ps

½ period of 1 GHz

Zero Delay

Between Input Clock Edge on REFA or

REFB to ZD_IN Input Clock Edge,

External Zero Delay Mode

150

500

ps

PLL1 settings: PFD = 7.68 MHz, ICP = 63.5 µA, RZERO = 10 kΩ,

antibacklash pulse width is at maximum, BW = 40 Hz,

REFA and ZD_IN are set to differential mode

JITTER AND NOISE CHARACTERISTICS

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT ABSOLUTE RMS TIME JITTER

Application example based on a typical setup

(see Table 3); f = 122.88 MHz

LVPECL Mode, HSTL Mode, LVDS Mode

125

fs

Integrated BW = 200 kHz to 5 MHz

136

fs

Integrated BW = 200 kHz to 10 MHz

169

fs

Integrated BW = 12 kHz to 20 MHz

212

fs

Integrated BW = 10 kHz to 61 MHz

223

fs

Integrated BW = 1 kHz to 61 MHz

PLL2 CHARACTERISTICS

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO (ON CHIP)

Frequency Range

3600

4000

MHz

Gain

45

MHz/V

PLL2 FIGURE OF MERIT (FOM)

−226

dBc/Hz

MAXIMUM PFD FREQUENCY

High is the initial PLL1 antibacklash pulse width setting.

The user must program Register 0x019[4] = 1b to enable

SPI control of the antibacklash pulse width to the

setting defined in Register 0x0F2[3:2] and Table 47.

Antibacklash Pulse Width

Minimum

259

MHz

Low

200

MHz

High

135

MHz

Maximum

80

MHz

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