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AD9524BCPZ Datasheet(PDF) 7 Page - Analog Devices |
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AD9524BCPZ Datasheet(HTML) 7 Page - Analog Devices |
7 / 56 page Data Sheet AD9524 Rev. F | Page 7 of 56 Parameter Min Typ Max Unit Test Conditions/Comments Input Capacitance 1 pF Duty Cycle Duty cycle bounds are set by pulse width high and pulse width low Pulse Width Low 1.6 ns Pulse Width High 1.6 ns OSC_CTRL OUTPUT CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT VOLTAGE High VDD3_PLL1 − 0.15 V RLOAD > 20 kΩ Low 150 mV REF_TEST INPUT CHARACTERISTICS Table 6. Parameter Min Typ Max Unit Test Conditions/Comments REF_TEST INPUT Input Frequency Range 250 MHz Input High Voltage 2.0 V Input Low Voltage 0.8 V PLL1 CHARACTERISTICS Table 7. Parameter Min Typ Max Unit Test Conditions/Comments PLL1 FIGURE OF MERIT (FOM) −226 dBc/Hz MAXIMUM PFD FREQUENCY High is the initial PLL1 antibacklash pulse width setting. The user must program Register 0x019[4] = 1b to enable SPI control of the antibacklash pulse width to the setting defined in Register 0x019[3:2] and Table 40. Antibacklash Pulse Width Minimum 130 MHz Low 90 MHz High 65 MHz Maximum 45 MHz PLL1 OUTPUT CHARACTERISTICS Table 8. Parameter1 Min Typ Max Unit Test Conditions/Comments MAXIMUM OUTPUT FREQUENCY 250 MHz Rise/Fall Time (20% to 80%) 387 665 ps 15 pF load Duty Cycle 45 50 55 % f = 250 MHz OUTPUT VOLTAGE HIGH Output driver static VDD3_PLL1 − 0.25 V Load current = 10 mA VDD3_PLL1 − 0.1 V Load current = 1 mA OUTPUT VOLTAGE LOW Output driver static 0.2 V Load current = 10 mA 0.1 V Load current = 1 mA 1 CMOS driver strength = strong (see Table 53). |
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